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hanchenye-llvm-project/llvm/test/CodeGen/CellSPU/bigstack.ll

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From Kalle Raiskila: "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
2010-03-30 01:38:47 +08:00
; RUN: llc < %s -march=cellspu -o %t1.s
Have SPU handle halfvec stores aligned by 8 bytes. llvm-svn: 110576
2010-08-10 00:33:00 +08:00
; RUN: grep lqx %t1.s | count 3
; RUN: grep il %t1.s | grep -v file | count 5
; RUN: grep stqx %t1.s | count 1
From Kalle Raiskila: "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
2010-03-30 01:38:47 +08:00
define i32 @bigstack() nounwind {
entry:
%avar = alloca i32
%big_data = alloca [2048 x i32]
store i32 3840, i32* %avar, align 4
br label %return
return:
%retval = load i32* %avar
ret i32 %retval
}