88 lines
3.2 KiB
YAML
88 lines
3.2 KiB
YAML
# RUNTIME configuration for the FireSim Simulation Manager
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# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params.
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run_farm:
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# managerinit replace start
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base_recipe: run-farm-recipes/aws_ec2.yaml
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# Uncomment and add args to override defaults.
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# Arg structure should be identical to the args given
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# in the base_recipe.
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#recipe_arg_overrides:
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# <ARG>: <OVERRIDE>
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# managerinit replace end
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metasimulation:
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metasimulation_enabled: false
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# vcs or verilator. use vcs-debug or verilator-debug for waveform generation
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metasimulation_host_simulator: verilator
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# plusargs passed to the simulator for all metasimulations
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metasimulation_only_plusargs: "+fesvr-step-size=128 +max-cycles=100000000"
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# plusargs passed to the simulator ONLY FOR vcs metasimulations
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metasimulation_only_vcs_plusargs: "+vcs+initreg+0 +vcs+initmem+0"
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target_config:
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topology: no_net_config
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no_net_num_nodes: 1
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link_latency: 6405
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switching_latency: 10
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net_bandwidth: 200
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profile_interval: -1
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# This references a section from config_hwdb.yaml for fpga-accelerated simulation
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# or from config_build_recipes.yaml for metasimulation
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# In homogeneous configurations, use this to set the hardware config deployed
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# for all simulators
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default_hw_config: firesim_rocket_quadcore_no_nic_l2_llc4mb_ddr3
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# Advanced: Specify any extra plusargs you would like to provide when
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# booting the simulator (in both FPGA-sim and metasim modes). This is
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# a string, with the contents formatted as if you were passing the plusargs
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# at command line, e.g. "+a=1 +b=2"
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plusarg_passthrough: ""
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tracing:
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enable: no
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# Trace output formats. Only enabled if "enable" is set to "yes" above
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# 0 = human readable; 1 = binary (compressed raw data); 2 = flamegraph (stack
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# unwinding -> Flame Graph)
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output_format: 0
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# Trigger selector.
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# 0 = no trigger; 1 = cycle count trigger; 2 = program counter trigger; 3 =
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# instruction trigger
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selector: 1
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start: 0
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end: -1
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autocounter:
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read_rate: 0
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workload:
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workload_name: linux-uniform.json
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terminate_on_completion: no
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suffix_tag: null
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host_debug:
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# When enabled (=yes), Zeros-out FPGA-attached DRAM before simulations
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# begin (takes 2-5 minutes).
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# In general, this is not required to produce deterministic simulations on
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# target machines running linux. Enable if you observe simulation non-determinism.
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zero_out_dram: no
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# If disable_synth_asserts: no, simulation will print assertion message and
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# terminate simulation if synthesized assertion fires.
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# If disable_synth_asserts: yes, simulation ignores assertion firing and
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# continues simulation.
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disable_synth_asserts: no
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# DOCREF START: Synthesized Prints
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synth_print:
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# Start and end cycles for outputting synthesized prints.
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# They are given in terms of the base clock and will be converted
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# for each clock domain.
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start: 0
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end: -1
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# When enabled (=yes), prefix print output with the target cycle at which the print was triggered
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cycle_prefix: yes
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# DOCREF END: Synthesized Prints
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