FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation

Contents

1. Using FireSim
2. What is FireSim?
3. What can I simulate with FireSim?
4. Need help?
5. Contributing
6. Publications

Using FireSim

To get started with using FireSim, see the tutorials on the FireSim documentation site: https://docs.fires.im/. You can also find slides from tutorials that we run at various conferences/events here: https://fires.im/tutorial/.

Another good overview (in video format) is our tutorial from the Chisel Community Conference on YouTube.

What is FireSim?

FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). FireSim is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley. You can learn more about FireSim in the following places:

• FireSim website: https://fires.im
• FireSim ISCA 2018 Paper: Paper PDF | IEEE Xplore | ACM DL | BibTeX | Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.
• FireSim documentation: https://docs.fires.im
• FireSim (+Chipyard) Tutorial: https://fires.im/tutorial/
• Scala API Documentation: https://fires.im/firesim/latest/api/
• Two-minute lightning talk from ISCA 2018 (FireSim simulating a datacenter): YouTube
• Chisel Community Conference Tutorial: YouTube
• Updates/News: Changelog | FireSim Blog | Twitter

What can I simulate with FireSim?

FireSim can simulate arbitrary hardware designs written in Chisel. With FireSim, you can write your own RTL (processors, accelerators, etc.) and run it at near-FPGA-prototype speeds on cloud FPGAs, while obtaining cycle-accurate performance results (i.e. matching what you would find if you taped-out a chip). Depending on the hardware design and the simulation scale, FireSim simulations run at 10s to 100s of MHz. You can also integrate custom software models for components that you don't want/need to write as RTL.

FireSim was originally developed to simulate datacenters by combining open RTL for RISC-V processors with a custom cycle-accurate network simulation. By default, FireSim provides all the RTL and models necessary to cycle-exactly simulate from one to thousands of multi-core compute nodes, derived directly from silicon-proven and open target-RTL (RISC-V Rocket Chip and BOOM), with an optional cycle-accurate network simulation tying them together. FireSim also provides a Linux distribution that is compatible with the RISC-V systems it simulates and automates the process of including new workloads into this Linux distribution. These simulations run fast enough to interact with Linux on the simulated system at the command line, like a real computer. Users can even SSH into simulated systems in FireSim and access the Internet from within them.

Head to the FireSim Website to learn more.

Need help?

• Join the FireSim Mailing list: https://groups.google.com/forum/#!forum/firesim
• Post an issue on this repo
• Follow on Twitter for project updates: @firesimproject

Contributing

• See CONTRIBUTING.md

Publications

ISCA 2018: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

You can learn more about FireSim in our ISCA 2018 paper, which covers the overall FireSim infrastructure and large distributed simulations of networked clusters. This paper was selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. In proceedings of the 45th International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.

Paper PDF | IEEE Xplore | ACM DL | BibTeX

FPGA 2019: FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

Our paper from FPGA 2019 details the DRAM model used in FireSim:

David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, FASED: FPGA-Accelerated Simulation and Evaluation of DRAM, In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2018.

Paper PDF | ACM DL | BibTeX

IEEE Micro Top Picks of 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

This article discusses several updates since the FireSim ISCA 2018 paper:

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.

Article PDF

ICCAD 2019: Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Our paper describing FireSim's Compiler, Golden Gate:

Albert Magyar, David T. Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović, Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes, In proceedings of the 39th International Conference on Computer-Aided Design (ICCAD '19), Westminster, CO, November 2019.

Paper PDF

ASPLOS 2020: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design

Our paper to appear in ASPLOS 2020 discusses system-level profiling features in FireSim:

Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design, In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Lausanne, Switzerland, March 2020.

Paper PDF

IEEE MICRO 2021: Accessible, FPGA Resource-Optimized Simulation of Multi-Clock Systems in FireSim

In this special issue, we describe the automated instance-multithreading optimization and support for multiple clock domains in the simulated target.

David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolić, Jonathan Bachrach, Krste Asanović. Accessible, FPGA Resource-Optimized Simulation of Multi-Clock Systems in FireSim. In IEEE Micro Volume: 41, Issue: 4, July-Aug. 1 2021

Article PDF

You can find other publications, including publications that use FireSim on the FireSim Website.