260 lines
14 KiB
Plaintext
260 lines
14 KiB
Plaintext
version = 3.0.0
|
|
|
|
project {
|
|
git = true,
|
|
includePaths = [
|
|
"glob:**.scala"
|
|
]
|
|
excludePaths = [
|
|
"glob:**firesim-lib/src/main/scala/bridges/BlockDevBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/DromajoBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/GroundTestBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/TSIBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/SimpleNICBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/TracerVBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/bridges/UARTBridge.scala",
|
|
"glob:**firesim-lib/src/main/scala/configs/CompilerConfigs.scala",
|
|
"glob:**firesim-lib/src/main/scala/configs/FASEDTargetConfigs.scala",
|
|
"glob:**firesim-lib/src/main/scala/passes/AsyncResetReg.scala",
|
|
"glob:**firesim-lib/src/main/scala/passes/ILATopWiring.scala",
|
|
"glob:**firesim-lib/src/main/scala/util/Configs.scala",
|
|
"glob:**firesim-lib/src/test/scala/EmitCIElaborationScript.scala",
|
|
"glob:**midas/src/main/scala/junctions/Nasti2AXI4.scala",
|
|
"glob:**midas/src/main/scala/junctions/ReorderQueue.scala",
|
|
"glob:**midas/src/main/scala/junctions/addrmap.scala",
|
|
"glob:**midas/src/main/scala/junctions/nasti.scala",
|
|
"glob:**midas/src/main/scala/midas/Config.scala",
|
|
"glob:**midas/src/main/scala/midas/FPGAQoRShimGenerator.scala",
|
|
"glob:**midas/src/main/scala/midas/SynthUnitTests.scala",
|
|
"glob:**midas/src/main/scala/midas/core/CPUManagedStreamEngine.scala",
|
|
"glob:**midas/src/main/scala/midas/core/Channel.scala",
|
|
"glob:**midas/src/main/scala/midas/core/Interfaces.scala",
|
|
"glob:**midas/src/main/scala/midas/core/LIBDNUnitTest.scala",
|
|
"glob:**midas/src/main/scala/midas/core/SimUtils.scala",
|
|
"glob:**midas/src/main/scala/midas/core/SimWrapper.scala",
|
|
"glob:**midas/src/main/scala/midas/core/StreamAllocator.scala",
|
|
"glob:**midas/src/main/scala/midas/core/StreamEngine.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/BankConflictModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/DramCommon.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/EgressUnit.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/FASEDMemoryTimingModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/FIFOMASModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/FRFCFSModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/IngressUnit.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/Interfaces.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/LastLevelCache.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/LatencyBandwidthPipe.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/RuntimeConfGenerator.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/TimingModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/TransactionSchedulers.scala",
|
|
"glob:**midas/src/main/scala/midas/models/dram/Util.scala",
|
|
"glob:**midas/src/main/scala/midas/models/sram/AsyncMemModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/sram/BankedAsyncMemModel.scala",
|
|
"glob:**midas/src/main/scala/midas/models/sram/ModelGenerator.scala",
|
|
"glob:**midas/src/main/scala/midas/models/sram/RegfileModel.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/AssertionSynthesis.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/AutoCounterTransform.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/BridgeTopWiring.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/ClockSourceFinder.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/CoerceAsyncToSyncReset.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/EnableAndRunDedupOnce.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/ExtractBridges.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/Fame1Transform.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/FindClockSources.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/MidasTransforms.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/PreLinkRenaming.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/PrintSynthesis.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/RemoveTrivialPartialConnects.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/RunConvertAssertsEarly.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/SimplifyMems.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/SimulationMapping.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/StroberUtils.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/TargetClockAnalysis.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/TriggerWiring.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/UpdateBridgeClockInfo.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/Utils.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/WriteXDCFile.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/AddRemainingFanoutAnnotations.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/Annotations.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/ChannelExcision.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/ConnectHostClock.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/EmitAndWrapRAMModels.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/ExtractModel.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/FAMEDefaults.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/FAMETransform.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/FAMEUtils.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/FindDefaultClocks.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/ImplementThreadedMems.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/InferModelPorts.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/LabelMultiThreadedInstances.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/LabelSRAMModels.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/MultiThreadFAME5Models.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/MultiThreader.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/MuxingMultithreader.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/PatientSSMTransformers.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/PromotePassthroughConnections.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/PromoteSubmodule.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/RTLUtils.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/TrivialChannelExcision.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/WrapTop.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/fame/package.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/package.scala",
|
|
"glob:**midas/src/main/scala/midas/passes/xilinx/package.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/AddDerivedAnnotations.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/Annotations.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/Checks.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/GoldenGateCli.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/GoldenGateFileEmission.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/GoldenGateStage.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/RuntimeConfigGenerationPhase.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/RuntimeConfigGeneratorCli.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/RuntimeConfigGeneratorStage.scala",
|
|
"glob:**midas/src/main/scala/midas/stage/phases/CreateParametersInstancePhase.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/AXI4AddressTranslation.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/AXI4Printf.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/AXI4TieOff.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/AssertBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/AutoCounterBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/Bridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/BridgeAnnotations.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/ChannelizedHostPort.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/ClockBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/CppGeneration.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/FuzzingUIntSource.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/HostPort.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/LoadMem.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/Master.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/PeekPokeIO.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/PrintBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/ResetPulseBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/SerializationUtils.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/TerminationBridge.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/UsesBridgeStreams.scala",
|
|
"glob:**midas/src/main/scala/midas/widgets/UsesHostDRAM.scala",
|
|
"glob:**midas/src/test/scala/firrtl/testutils/FirrtlSpec.scala",
|
|
"glob:**midas/src/test/scala/firrtl/testutils/LeanTransformSpec.scala",
|
|
"glob:**midas/src/test/scala/firrtl/testutils/PassTests.scala",
|
|
"glob:**midas/src/test/scala/midas/BridgeTopWiringSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/CoerceAsyncToSyncResetSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/FAMEAnnotationSerializationSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/FindClockSourcesSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/FooTransform.scala",
|
|
"glob:**midas/src/test/scala/midas/passes/WriteXDCFileSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/stage/AddDerivedAnnotationsSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/stage/ChecksSpec.scala",
|
|
"glob:**midas/src/test/scala/midas/widgets/ChannelizedHostPortIOSpec.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/ElaborateChiselSubCircuit.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/PassthroughBlocker.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/annotations.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/xdc/RAMStyleHint.scala",
|
|
"glob:**midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala",
|
|
"glob:**midas/targetutils/src/test/scala/ElaborationUtils.scala",
|
|
"glob:**midas/targetutils/src/test/scala/FpgaDebugSpec.scala",
|
|
"glob:**midas/targetutils/src/test/scala/PerfCounterSpec.scala",
|
|
"glob:**midas/targetutils/src/test/scala/RAMStyleHintSpec.scala",
|
|
"glob:**src/main/scala/fasedtests/AXI4Fuzzer.scala",
|
|
"glob:**src/main/scala/fasedtests/Config.scala",
|
|
"glob:**src/main/scala/midasexamples/AssertModule.scala",
|
|
"glob:**src/main/scala/midasexamples/AssertTorture.scala",
|
|
"glob:**src/main/scala/midasexamples/AutoCounter32bRollover.scala",
|
|
"glob:**src/main/scala/midasexamples/AutoCounterModule.scala",
|
|
"glob:**src/main/scala/midasexamples/AutoCounterValidator.scala",
|
|
"glob:**src/main/scala/midasexamples/Config.scala",
|
|
"glob:**src/main/scala/midasexamples/EnableShiftRegister.scala",
|
|
"glob:**src/main/scala/midasexamples/GCD.scala",
|
|
"glob:**src/main/scala/midasexamples/GlobalResetConditionTests.scala",
|
|
"glob:**src/main/scala/midasexamples/InstanceNameHelper.scala",
|
|
"glob:**src/main/scala/midasexamples/MultiReg.scala",
|
|
"glob:**src/main/scala/midasexamples/MultiRegfile.scala",
|
|
"glob:**src/main/scala/midasexamples/MultiSRAM.scala",
|
|
"glob:**src/main/scala/midasexamples/MulticlockAutoCounterModule.scala",
|
|
"glob:**src/main/scala/midasexamples/MulticlockPrintfModule.scala",
|
|
"glob:**src/main/scala/midasexamples/NestedModels.scala",
|
|
"glob:**src/main/scala/midasexamples/Parity.scala",
|
|
"glob:**src/main/scala/midasexamples/PassthroughModels.scala",
|
|
"glob:**src/main/scala/midasexamples/PointerChaser.scala",
|
|
"glob:**src/main/scala/midasexamples/PrintfModule.scala",
|
|
"glob:**src/main/scala/midasexamples/Regfile.scala",
|
|
"glob:**src/main/scala/midasexamples/ResetPulseBridgeTest.scala",
|
|
"glob:**src/main/scala/midasexamples/ResetShiftRegister.scala",
|
|
"glob:**src/main/scala/midasexamples/Risc.scala",
|
|
"glob:**src/main/scala/midasexamples/RiscSRAM.scala",
|
|
"glob:**src/main/scala/midasexamples/ShiftRegister.scala",
|
|
"glob:**src/main/scala/midasexamples/Stack.scala",
|
|
"glob:**src/main/scala/midasexamples/Termination.scala",
|
|
"glob:**src/main/scala/midasexamples/TriggerPredicatedPrintf.scala",
|
|
"glob:**src/main/scala/midasexamples/TriggerWiringModule.scala",
|
|
"glob:**src/main/scala/midasexamples/TrivialMulticlock.scala",
|
|
"glob:**src/main/scala/midasexamples/TwoAdders.scala",
|
|
"glob:**src/main/scala/midasexamples/Util.scala",
|
|
"glob:**src/main/scala/midasexamples/VerilogAccumulator.scala",
|
|
"glob:**src/main/scala/midasexamples/WireInterconnect.scala",
|
|
]
|
|
}
|
|
|
|
maxColumn = 120
|
|
align.preset = most
|
|
continuationIndent.defnSite = 2
|
|
assumeStandardLibraryStripMargin = true
|
|
|
|
docstrings.style = SpaceAsterisk
|
|
|
|
lineEndings = preserve
|
|
optIn.configStyleArguments = true
|
|
danglingParentheses.preset = true
|
|
verticalMultiline.excludeDanglingParens = []
|
|
trailingCommas = multiple
|
|
|
|
align.tokens."+" = [
|
|
{
|
|
code = "=",
|
|
owners=[{regex="Term.Param|Defn|Term.Assign"}]
|
|
},
|
|
{
|
|
code = ":",
|
|
owners = [{regex="Term.Param|Decl.Def"}]
|
|
},
|
|
{
|
|
code = ":="
|
|
},
|
|
{
|
|
code = "<>"
|
|
},
|
|
{
|
|
code = ":*="
|
|
},
|
|
{
|
|
code = ":=*"
|
|
},
|
|
{
|
|
code = ":*=*"
|
|
},
|
|
{
|
|
code = ":<="
|
|
},
|
|
{
|
|
code = ":=>"
|
|
},
|
|
{
|
|
code = ":<>"
|
|
}
|
|
]
|
|
|
|
includeCurlyBraceInSelectChains = true
|
|
includeNoParensInSelectChains = false
|
|
optIn.breakChainOnFirstMethodDot = true
|
|
newlines.alwaysBeforeCurlyBraceLambdaParams = false
|
|
newlines.alwaysBeforeMultilineDef = false
|
|
newlines.implicitParamListModifierPrefer = before
|
|
|
|
verticalMultiline.atDefnSite = true
|
|
|
|
optIn.annotationNewlines = true
|
|
|
|
rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]
|