89 lines
3.2 KiB
Makefile
89 lines
3.2 KiB
Makefile
# See LICENSE for license details.
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#############################
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# FPGA Build Initialization #
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#############################
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platforms_dir := $(abspath $(firesim_base_dir)/../platforms)
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ifeq ($(PLATFORM), vitis)
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board_dir := $(platforms_dir)/vitis
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else ifeq ($(PLATFORM), xilinx_alveo_u250)
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board_dir := $(platforms_dir)/xilinx_alveo_u250
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else ifeq ($(PLATFORM), xilinx_alveo_u280)
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board_dir := $(platforms_dir)/xilinx_alveo_u280
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else ifeq ($(PLATFORM), xilinx_alveo_u200)
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board_dir := $(platforms_dir)/xilinx_alveo_u200
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else ifeq ($(PLATFORM), xilinx_vcu118)
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board_dir := $(platforms_dir)/xilinx_vcu118/garnet-firesim
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else ifeq ($(PLATFORM), rhsresearch_nitefury_ii)
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board_dir := $(platforms_dir)/rhsresearch_nitefury_ii/NiteFury-and-LiteFury-firesim/Sample-Projects/Project-0
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else ifeq ($(PLATFORM), f1)
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board_dir := $(platforms_dir)/f1/aws-fpga/hdk/cl/developer_designs
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else
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$(error Invalid PLATFORM used: $(PLATFORM))
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endif
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fpga_work_dir := $(board_dir)/cl_$(name_quintuplet)
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fpga_build_dir := $(fpga_work_dir)/build
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verif_dir := $(fpga_work_dir)/verif
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repo_state := $(fpga_work_dir)/design/repo_state
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fpga_driver_dir:= $(fpga_work_dir)/driver
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fpga_delivery_dir := $(fpga_work_dir)/design
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ifeq ($(PLATFORM), rhsresearch_nitefury_ii)
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fpga_delivery_dir := $(fpga_work_dir)/Nitefury-II/project/project.srcs/sources_1/imports/HDL
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endif
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# Enumerates the subset of generated files that must be copied over for FPGA compilation
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fpga_delivery_files = $(addprefix $(fpga_delivery_dir)/$(BASE_FILE_NAME), \
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.sv .defines.vh \
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.synthesis.xdc .implementation.xdc)
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# Files used to run FPGA-level metasimulation
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fpga_sim_delivery_files = $(fpga_driver_dir)/$(DESIGN)-$(PLATFORM)
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$(fpga_work_dir)/stamp: $(shell find $(board_dir)/cl_firesim -name '*')
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mkdir -p $(driver_dir) #Could just set up in the shell project
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cp -rf $(board_dir)/cl_firesim -T $(fpga_work_dir)
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touch $@
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$(repo_state): $(simulator_verilog) $(fpga_work_dir)/stamp
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$(firesim_base_dir)/../scripts/repo_state_summary.sh > $(repo_state)
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$(fpga_delivery_dir)/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
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cp -f $(GENERATED_DIR)/*.ipgen.tcl $(@D) || true
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cp -f $(GENERATED_DIR)/$(@F) $@
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$(fpga_driver_dir)/$(BASE_FILE_NAME)%: $(simulator_verilog) $(fpga_work_dir)/stamp
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mkdir -p $(@D)
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cp -f $(GENERATED_DIR)/$(@F) $@
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$(fpga_driver_dir)/$(DESIGN)-$(PLATFORM): $($(PLATFORM))
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mkdir -p $(@D)
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cp -f $< $@
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# Goes as far as setting up the build directory without running the cad job
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# Used by the manager before passing a build to a remote machine
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replace-rtl: $(fpga_delivery_files) $(fpga_sim_delivery_files)
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.PHONY: replace-rtl
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$(firesim_base_dir)/scripts/checkpoints/$(target_sim_tuple): $(fpga_work_dir)/stamp
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mkdir -p $(@D)
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ln -sf $(fpga_build_dir)/checkpoints/to_aws $@
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# Runs a local fpga-bitstream build. Strongly consider using the manager instead.
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.PHONY: fpga
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fpga: export CL_DIR := $(fpga_work_dir)
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fpga: $(fpga_delivery_files) $(base_dir)/scripts/checkpoints/$(target_sim_tuple)
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cd $(fpga_build_dir)/scripts && ./aws_build_dcp_from_cl.sh -notify
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#########################
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# Cleaning Recipes #
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#########################
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.PHONY: cleanfpga
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cleanfpga:
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rm -rf $(fpga_work_dir)
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