13 lines
342 B
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13 lines
342 B
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.. |fpga_name| replace:: Xilinx VCU118
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.. |bit_type| replace:: ``bitstream_tar``
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.. |build_type| replace:: Xilinx Vivado
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.. include:: Intro-Template.rst
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.. toctree::
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:maxdepth: 3
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Initial-Setup/Xilinx-Alveo-U250
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Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U250
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Building-a-FireSim-Bitstream/Xilinx-Alveo-U250
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