131 lines
4.9 KiB
Bash
Executable File
131 lines
4.9 KiB
Bash
Executable File
#!/usr/bin/env bash
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# This script runs a RISC-V assembly test in RTL simulation at the three
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# supported abstraction levels and captures the necessary portions of the log
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# to calculate simulation rates
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#
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# Abstraction levels:
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# Target -> Just the target RTL
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# MIDAS -> The target post-transformations, fpga-hosted models & widgets
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# FPGA -> The whole RTL design pre-synthesis
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#
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# This requires a VCS license.
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# Berkeley users: If running on millenium machines, source scripts/setup_vcsmx_env.sh
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# The ISA test to run
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TEST=rv64ui-v-add
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#TEST=rv64ui-p-simple
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# The file into which we dump all the relevant pieces of simulation log. Some
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# post-processing is still required.
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REPORT_FILE=$(pwd)/runtime.rpt
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MAKE_THREADS=4
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cd $(dirname $0)/..
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firesim_root=$(pwd)
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test_path=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/$TEST
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echo -e "FireSim RTL Simulation Execution Rates\n" > $REPORT_FILE
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################################################################################
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# TARGET level
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################################################################################
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export DESIGN=FireSimNoNIC
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export TARGET_CONFIG=FireSimRocketChipConfig
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export PLATFORM_CONFIG=BaseF1Config
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export SIM_ARGS=+verbose
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export TIME="%C %E real, %U user, %S sys"
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for optlevel in 0 1 2
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do
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echo -e "\nVerilator TARGET-level Simulation, -O${optlevel}\n" >> $REPORT_FILE
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## Verilator
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cd $firesim_root/target-design/chipyard/verisim
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sim=simulator-example-DefaultExampleConfig
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# Hack...
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sed -i "s/-O[0-3]/-O${optlevel}/" Makefile
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make clean
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/usr/bin/time -a -o $REPORT_FILE make
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/usr/bin/time -a -o $REPORT_FILE make debug
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echo -e "\nNo Waves\n" >> $REPORT_FILE
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/usr/bin/time -a -o $REPORT_FILE ./$sim $SIM_ARGS $test_path &> nowaves.log
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tail nowaves.log >> $REPORT_FILE
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/usr/bin/time -a -o $REPORT_FILE ./$sim-debug $SIM_ARGS -vtest.vcd $test_path &> waves.log
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echo -e "\nWaves Enabled\n" >> $REPORT_FILE
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tail waves.log >> $REPORT_FILE
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done
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echo -e "\nTarget-level VCS\n" >> $REPORT_FILE
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cd $firesim_root/target-design/chipyard/vsim/
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sim=simv-example-DefaultExampleConfig
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS debug
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echo -e "\nNo Waves\n" >> $REPORT_FILE
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/usr/bin/time -a -o $REPORT_FILE ./$sim $SIM_ARGS $test_path &> nowaves.log
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tail nowaves.log >> $REPORT_FILE
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echo -e "\nWaves Enabled\n" >> $REPORT_FILE
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/usr/bin/time -a -o $REPORT_FILE ./$sim-debug $SIM_ARGS $test_path &> waves.log
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tail waves.log >> $REPORT_FILE
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################################################################################
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## MIDAS level
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################################################################################
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ml_output_dir=$firesim_root/sim/output/f1/$DESIGN-$TARGET_CONFIG-$PLATFORM_CONFIG
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test_symlink=$ml_output_dir/$TEST
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for optlevel in 0 1 2
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do
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echo -e "\nMIDAS-level Simulation, -O${optlevel}\n" >> $REPORT_FILE
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cd $firesim_root/sim
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make clean
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make -j$MAKE_THREADS
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS VERILATOR_CXXOPTS=-O${optlevel} verilator
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS VERILATOR_CXXOPTS=-O${optlevel} verilator-debug
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS VCS_CXXOPTS=-O${optlevel} vcs
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/usr/bin/time -a -o $REPORT_FILE make -j$MAKE_THREADS VCS_CXXOPTS=-O${optlevel} vcs-debug
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mkdir -p $ml_output_dir
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# Symlink it twice so we have unique targets for vcs and verilator
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ln -sf $test_path $ml_output_dir/$TEST
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ln -sf $test_path $ml_output_dir/$TEST-vcs
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echo -e "\nWaves Off, -O${optlevel}\n" >> $REPORT_FILE
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make EMUL=vcs ${test_symlink}-vcs.out
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make ${test_symlink}.out
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grep -Eo "simulation speed = .*" $ml_output_dir/*out >> $REPORT_FILE
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echo -e "\nWaves On, -O${optlevel}\n" >> $REPORT_FILE
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make EMUL=vcs ${test_symlink}-vcs.vpd
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make ${test_symlink}.vpd
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grep -Eo "simulation speed = .*" $ml_output_dir/*out >> $REPORT_FILE
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done
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################################################################################
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# FPGA level
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################################################################################
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# Unlike the other levels, the driver and dut communicate through pipes
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cd $firesim_root/sim
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echo -e "\nFPGA-level XSIM - Waves On\n" >> $REPORT_FILE
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make xsim
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make xsim-dut | tee dut.out &
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# Wait for the dut to come up; Compilation time is long.
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while [[ $(grep driver_to_xsim dut.out) == '' ]]; do sleep 1; done
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make run-xsim SIM_BINARY=$test_path &> driver.out
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# These are too slow for the reported simulation rate to be non-zero; so tail
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tail driver.out >> $REPORT_FILE
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echo -e "\nFPGA-level VCS - Waves On\n" >> $REPORT_FILE
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make xsim
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make xsim-dut VCS=1 | tee vcs-dut.out &
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# Wait for the dut to come up; Compilation time is long.
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while [[ $(grep driver_to_xsim vcs-dut.out) == '' ]]; do sleep 1; done
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make run-xsim SIM_BINARY=$test_path &> vcs-driver.out
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# These are too slow for the reported simulation rate to be non-zero; so tail
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tail vcs-driver.out >> $REPORT_FILE
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