![]() Includes improvements to post-synth simulations: - Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures - Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis - The harness now explicitly waits for GSR - Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available. Co-authored-by: Nandor Licker <nandorl@sifive.com> |
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.. | ||
.gitignore | ||
create-afi.py | ||
create-bucket.py | ||
describe-afi.sh | ||
load-fpga.sh | ||
synth_fpga.tcl | ||
synth_fpga.xdc |