24 lines
809 B
Systemverilog
24 lines
809 B
Systemverilog
// Most of the verilog affected by these `defines should be removed
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// by the verilog preprocesor when in synthesis. I'm adding the extra guard
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// here to be explicit.
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`ifndef SYNTHESIS
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// Setting these an avoids X-prop issues for uninitialized state in
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// Chisel-emitted verilog
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`define RANDOMIZE_MEM_INIT
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`define RANDOMIZE_REG_INIT
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`define RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE_INVALID_ASSIGN
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// This populates anything that would be randomized with assignment to 0
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// Note: Calls to $random appear to break vitis hardware emulation, this both
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// works around that, and provides a somewhat better model of the FPGA.
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`define RANDOM 1'b0
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// TODO: determine sensible values for these. Need a path through the linked
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// design hierarchy to reset.
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`define PRINTF_COND 1'b1
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`define STOP_COND 1'b1
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`endif
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