42 lines
2.0 KiB
INI
42 lines
2.0 KiB
INI
# Configuration settings used only for bitstream builds
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# This is the "hw" target of v++
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[vivado]
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# These match the timing strategy used in aws-fpga
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prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=ExtraNetDelay_high
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prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-tns_cleanup}
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prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.{STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-sll_reg_hold_fix}
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# See Note 1
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# Note 1. There was .5ns skew between the source and destination clock on a
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# path that spanned two SLRs, just as the critical warning gauged.. I've
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# enabled -sll_reg_hold_fix since for now, but this warrants further
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# investigation.
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#
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# WARNING: [Route 35-459] Router was unable to fix hold violation on 31 pins. This could be due to a combination of congestion, blockages and run-time limitations. Such pins are:
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# level0_i/level1/level1_i/ulp/ip_rs_axi_data_c2h_00/inst/b16.b_auto/m_areset_resp_reg_psap_11/D
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#
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# CRITICAL WARNING: [Physopt 32-954] Router is skipping hold fixing on SLR
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# crossing paths with direct Laguna TX to RX connection as the number of
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# violations exceeds the runtime threshold for this hold fixing in the router.
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#
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# Resolution: A large number of hold violations on direct Laguna TX to RX paths
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# is an indication of a clocking topology that causes larger than expected amount
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# of clock skew on SLR crossing paths. Please ensure that the registers
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# implementing the Laguna TX to RX connection are on the same clock net and the
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# root of the clock net is in the center of the device. You can also run
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# phys_opt_design with the -sll_reg_hold_fix option after route_design to attempt
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# fixing hold violations on these direct Laguna TX to RX paths with potentially
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# long runtime.
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