46 lines
1.8 KiB
ReStructuredText
46 lines
1.8 KiB
ReStructuredText
.. |fpga_name| replace:: (Experimental) Xilinx Alveo U250 Vitis-based
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.. |fpga_name_short| replace:: Xilinx Alveo U250
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.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html
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.. |flow_name| replace:: Vitis-based
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.. |build_type| replace:: Xilinx Vitis
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.. warning::
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⚠️ **We highly recommend using the XDMA-based U250 flow instead of this Vitis-based
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flow. You can find the XDMA-based flow here:** :ref:`u250-standard-flow`. The
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Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV,
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Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim
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features. If you're unsure, use the XDMA-based U250 flow instead:
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:ref:`u250-standard-flow`
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.. include:: Intro-Template.rst
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1. **FPGA Setup**: Installing the FPGA board and relevant software.
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2. **On-Premises Machine Setup**
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1. Setting up a "Manager Machine" from which you will coordinate building and
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deploying simulations locally.
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3. **Single-node simulation guide**: This guide walks you through the process of running
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a simulation locally on a single |fpga_name_short|, using a pre-built, public
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bitstream.
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4. **Building your own hardware designs guide (Chisel to FPGA Image)**: This guide walks
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you through the full process of taking Rocket Chip RTL and any custom RTL plugged
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into Rocket Chip and producing a FireSim bitstream to plug into your simulations.
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This automatically runs Chisel elaboration, FAME-1 Transformation, and the
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|build_type| FPGA flow.
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Generally speaking, you only need to follow Step 4 if you're modifying Chisel RTL or
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changing non-runtime configurable hardware parameters.
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.. toctree::
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:maxdepth: 3
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Initial-Setup/Xilinx-Vitis-FPGAs
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Running-Simulations/Running-Single-Node-Simulation-Xilinx-Vitis
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Building-a-FireSim-Bitstream/Xilinx-Vitis
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