33 lines
1.5 KiB
ReStructuredText
33 lines
1.5 KiB
ReStructuredText
.. |fpga_type| replace:: Xilinx Vitis-enabled U250
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.. |deploy_manager| replace:: VitisInstanceDeployManager
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.. |deploy_manager_code| replace:: ``VitisInstanceDeployManager``
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.. |runner| replace:: Xilinx XRT/Vitis
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.. |hwdb_entry_name| replace:: vitis_firesim_rocket_singlecore_no_nic
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.. warning::
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⚠️ **We highly recommend using the XDMA-based U250 flow instead of this Vitis-based
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flow. You can find the XDMA-based flow here:** :ref:`u250-standard-flow`. The
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Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV,
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Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim
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features. If you're unsure, use the XDMA-based U250 flow instead:
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:ref:`u250-standard-flow`
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.. include:: Running-Single-Node-Simulation-Vitis-Template.rst
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.. warning::
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In some cases, simulation may fail because you might need to update the |fpga_type|
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DRAM offset that is currently hard coded in both the FireSim |runner| driver code
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and platform shim. To verify this, run ``xclbinutil --info --input <YOUR_XCL_BIN>``,
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obtain the ``bank0`` ``MEM_DDR4`` offset. If it differs from the hardcoded
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``0x40000000`` given in driver code (``u250_dram_expected_offset`` variable in
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:gh-file-ref:`sim/midas/src/main/cc/simif_vitis.cc`) and platform shim
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(``araddr``/``awaddr`` offset in
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:gh-file-ref:`sim/midas/src/main/scala/midas/platform/VitisShim.scala`) replace both
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areas with the new offset given by ``xclbinutil`` and regenerate the bitstream.
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