27 lines
988 B
ReStructuredText
27 lines
988 B
ReStructuredText
.. |fpga_name| replace:: Xilinx Vitis-enabled U250
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.. |hwdb_entry_name| replace:: ``vitis_firesim_rocket_singlecore_no_nic``
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.. |hwdb_entry_name_non_code| replace:: vitis_firesim_rocket_singlecore_no_nic
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.. |builder_name| replace:: Xilinx Vitis
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.. |bit_builder_path| replace:: ``bit-builder-recipes/vitis.yaml``
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.. warning::
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⚠️ **We highly recommend using the XDMA-based U250 flow instead of this Vitis-based
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flow. You can find the XDMA-based flow here:** :ref:`u250-standard-flow`. The
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Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV,
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Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim
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features. If you're unsure, use the XDMA-based U250 flow instead:
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:ref:`u250-standard-flow`
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Building Your Own Hardware Designs
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==================================
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This section will guide you through building a |fpga_name| FPGA bitstream to run FireSim
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simulations.
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.. include:: Xilinx-All-Bitstream-Template.rst
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