31 lines
1.0 KiB
ReStructuredText
31 lines
1.0 KiB
ReStructuredText
.. |fpga_name| replace:: Xilinx Alveo U280
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.. |hwdb_entry_name| replace:: ``alveo_u280_firesim_rocket_singlecore_no_nic``
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.. |hwdb_entry_name_non_code| replace:: alveo_u280_firesim_rocket_singlecore_no_nic
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.. |builder_name| replace:: Xilinx Vivado
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.. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_alveo_u280.yaml``
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.. |vivado_with_version| replace:: Vivado 2021.1
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.. |vivado_version_number_only| replace:: 2021.1
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.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2021.1``
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.. |board_package_install| replace:: Download the ``au280`` board support package
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directory from https://github.com/Xilinx/open-nic-shell/tree/main/board_files/Xilinx
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and place the directory in
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``/tools/Xilinx/Vivado/2021.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/``.
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Building Your Own Hardware Designs
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==================================
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This section will guide you through building a |fpga_name| FPGA bitstream to run FireSim
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simulations.
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.. include:: Xilinx-XDMA-Build-Farm-Setup-Template.rst
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.. include:: Xilinx-All-Bitstream-Template.rst
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