54 lines
1.8 KiB
ReStructuredText
54 lines
1.8 KiB
ReStructuredText
.. _spike:
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Spike Co-simulation with BOOM designs
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=====================================
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Instead of using TracerV to provide a cycle-by-cycle trace of a target CPU's
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architectural state, you can use the `Spike co-simulator
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<https://github.com/riscv-software-src/riscv-isa-sim>`_ to verify the functionality of a
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BOOM design.
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.. note::
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This work currently only works for single core BOOM designs.
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.. note::
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Cospike only supports non block-device simulations at this time.
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.. _cospike-bridge:
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Building a Design with Cospike
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------------------------------
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In all FireChip designs, TracerV is included by default. To enable Cospike, you just
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need to add the Cospike bridge (``WithCospikeBridge``) to your BOOM target design config
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(default configs. located in
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``$CHIPYARD/generators/firechip/src/main/scala/TargetConfigs.scala``). An example
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configuration with Cospike is shown below:
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.. code-block:: scala
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class FireSimLargeBoomConfig extends Config(
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new WithCospikeBridge ++ // add Cospike bridge to simulation
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.LargeBoomV3Config)
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At this point, you should run the ``firesim buildbitstream`` command for the BOOM config
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wanted. At this point you are ready to run the simulation with Cospike by default
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enabled.
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Troubleshooting Cospike Simulations with Meta-Simulations
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---------------------------------------------------------
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If FPGA simulation fails with Cospike, you can use metasimulation to determine if your
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Cospike setup is correct. First refer to :ref:`metasimulation` for more information on
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metasimulation.
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.. note::
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Sometimes simulations in VCS will diverge unless a ``+define+RANDOM=0`` is added to
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the VCS flags in ``sim/midas/src/main/cc/rtlsim/Makefrag-vcs``.
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