d6de4ab565
vcu118 support throughout firesim
2023-05-06 17:09:18 -07:00
f6fc4ccfec
Intermediate changes [ci skip]
2023-05-04 23:35:56 -07:00
c231ca15f4
First attempt at bare Xilinx U250 support
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Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: Björn Gottschall <info@gottschall.no>
Co-authored-by: David Metz <david.c.metz@ntnu.no>
2023-05-03 01:07:15 -07:00
2081529fb6
Update Vitis docs | Bump FPGA platform to 2022.1
2023-01-20 11:06:40 -08:00
e83c4bb82a
Clean build-bitstream.sh's | Harmonize build arguments
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(cherry picked from commit f8479e6017b1d9cf0c26b4a4a3541d1493da4700)
2022-10-30 20:01:36 -07:00
aefbe7fb2d
Add initial python manager files ported for Vitis
2022-06-08 05:46:36 +00:00
3f91fa2c63
Update to new API | Address PR comments
2022-06-08 04:03:37 +00:00
e88661e250
Allow argument passing to bit builder
2022-06-08 03:37:20 +00:00
Sagar Karandikar