Jerry Zhao
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5f9bf2b42b
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Rename SerialBridge to TSIBridge
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2023-05-08 15:21:38 -07:00 |
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Nandor Licker
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797e6e41bc
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Introduced a full verilator/vcs/debug matrix (#1435)
This PR moves the paramterization of test harnesses to the toplevel.
Slightly re-wrote tests to avoid duplication of running logic.
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2023-02-19 11:31:03 +00:00 |
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Nandor Licker
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d194593ece
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Enabled scalafmt on more sources (#1429)
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2023-02-09 09:25:39 -08:00 |
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David Biancolin
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fdb5d6d439
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FPGA-managed bridge stream support in metasimulation (#1181)
* metasim-able FPGA-controlled bridge streams
* simif: Add a virtual method to permit doing streamengine init
* Remove unneeded vitis kernel def changes
* Address some of nandors comments
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2022-12-24 11:18:03 -05:00 |
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Russell Horvath
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0283f95bcd
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remove env script + plumb through bitbuilder
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2022-09-27 03:20:34 +00:00 |
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David Biancolin
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4fecf9a234
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Add scalafmt configuration and SBT plugin.
Excludes all existing files.
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2022-05-31 20:07:34 +00:00 |