6e993f5089
Fix wiring of unused ports ( #1437 )
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A previous PR set the values to 0, which is incorrect, however CI auto-merged the changes without blocking on the failure.
2023-02-22 10:57:29 +00:00
4b5840fca8
Do not materialize memory connections if the target does not use them ( #1431 )
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In line with the omission of managed stream engines and their associated connections
to the top-level, this PR also eliminates unused memory connections. The top-level
ports to the platform hardware are left unchanged. If no memories are used in the
target, the `LoadMem` widget is omitted.
2023-02-21 18:45:38 +00:00
84b1c3f900
Add option to F1 driver to load an AGFI ( #1434 )
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If the `+agfi=` option points to an AGFI, the image is loaded before the simulation starts.
2023-02-21 19:00:34 +02:00
797e6e41bc
Introduced a full verilator/vcs/debug matrix ( #1435 )
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This PR moves the paramterization of test harnesses to the toplevel.
Slightly re-wrote tests to avoid duplication of running logic.
2023-02-19 11:31:03 +00:00
9818dbcae3
Added a test for memory accesses ( #1433 )
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This PR fixes the invocation to `LoadMem` and adds a test for it.
The test performs memory read accesses through a TileLink node which goes to DRAM through a trivial FASED bridge.
Read requests from the driver are received through the `PeekPokeBridge` and are sent back to be printed to a file.
The test harness compares the file passed to loadmem with the results produced by this bridge, which should read all data back.
2023-02-18 20:14:42 +02:00
c6f72296aa
Do not materialize a stream engine if no streams are used ( #1430 )
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The stream engine is omitted from the design and the driver if there are no bridges relying on it.
This is very useful for debugging as it eliminates a lot of SystemVerilog generated from most small
designs and reduces the amount of gates synthesized for smaller tests.
2023-02-11 09:37:30 +02:00
bec25aaf19
Tests for existing TracerV bridge including trigger modes ( #1426 )
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* Tests for mode 0,1,2
* Test for mode 3 disabled until Issue #1428 is resolved
2023-02-09 11:40:04 -08:00
d194593ece
Enabled scalafmt on more sources ( #1429 )
2023-02-09 09:25:39 -08:00
30fd72bc7f
Remove `constructor.h` and replace it with a Scala-generated header ( #1398 )
2023-02-08 00:52:51 +02:00
abed23be29
Restored the runtime config generation phase ( #1425 )
2023-02-03 09:06:04 +02:00
6420252509
Removed auxiliary functions from simif_t ( #1424 )
2023-02-02 22:25:40 +02:00
9d3462ed13
Merge pull request #1392 from firesim/scala213
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Bump to latest rocket-chip/scala2.13
2023-02-01 14:30:09 -08:00
bf051c785f
Re-enabled timeout detection for harnesses ( #1423 )
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The changes got lost in rebases. This PR re-introduces them.
2023-02-01 19:21:02 +00:00
1a63bbe7c3
bump aws-fpga to remove bloat files in hdk/cl/examples + fix typo ( #1406 )
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* bump aws-fpga to remove bloat files + fix typo
2023-02-01 10:10:20 -08:00
2889818e7d
Removed the compiler-generated runtime config ( #1422 )
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The default arguments to FASED memory models are now passed alongside other FASED bridge arguments.
These defaults can be overriden by other args passed to the bridge driver or disabled when the raw hardware configuration is requested.
The manager can still pass an optional runtime config to the design to override arguments.
2023-02-01 19:19:00 +02:00
9ae4ed7f52
Passed memory offsets to genHeader ( #1416 )
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Instead of emitting a constant and referencing it by name in the header for
a bridge constructor, the memory mapping is passed alongside the base offset
for MMIO for bridge header emission to reference.
2023-02-01 10:47:14 +00:00
4d1876334e
Introduced a unique main to the simulation. ( #1368 )
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The main method centralizes more of the lifecycle of a simulation.
2023-02-01 10:40:08 +02:00
479242c068
Bump xclbin
2023-01-31 22:05:32 -08:00
d148b7380b
Bump agfis
2023-01-31 18:28:15 +00:00
2a5f0cfe70
Revert changing testOnly behavior
2023-01-30 23:30:17 -08:00
a1981c11ec
Merge remote-tracking branch 'origin/main' into scala213
2023-01-30 17:24:06 -08:00
e932316c9a
Bump chipyard
2023-01-30 15:13:26 -08:00
9bebd0a294
Bump CI log tail length to 300 lines
2023-01-30 14:16:20 -08:00
b191677aa4
Fix undriven signals in BlockDevDUT
2023-01-30 09:39:23 -08:00
0c2e8dd6bc
Fixed missing array include ( #1417 )
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Some versions of GCC/Clang complain, some do not. This includes the header.
2023-01-30 08:24:32 +02:00
4261f376d1
Bump CY
2023-01-29 16:31:45 -08:00
5bd55fde0e
Merge pull request #1412 from firesim/rhorvath/vitis-readme-additions
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Add reports and checkpoints section to vitis readme
2023-01-28 16:44:11 -08:00
a96ce0412d
Fix Vitis driver CI check ( #1415 )
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* Fix order of cd in Vitis driver CI
* Add PLATFORM flag to driver build
2023-01-28 14:43:45 +02:00
4f1edb5e93
Fix FireMarshal workload paths
2023-01-27 17:05:20 -08:00
5146d8a596
Fix CI by adding platform
2023-01-27 17:02:11 -08:00
5f5a219301
Fix Vitis driver build CI
2023-01-27 13:55:55 -08:00
e21107d288
Don't initialize FireMarshal in build-setup-nolog.sh
2023-01-27 13:52:18 -08:00
7af5bd9f67
Run Scala formatting
2023-01-27 13:52:18 -08:00
b5ac19d374
Update build-setup-nolog.sh
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Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
2023-01-27 13:52:18 -08:00
5124772441
Skip unnecessary chipyard setup steps
2023-01-27 13:52:18 -08:00
a6de5dd121
Fix midas AutoILA to not depend on set traversal ordering
2023-01-27 13:52:18 -08:00
395be41656
Bump chipyard
2023-01-27 13:52:18 -08:00
96ef6200fe
Bump chipyard.mk to scala 2.13
2023-01-27 13:52:18 -08:00
d384fc52bc
Fix testOnly rule
2023-01-27 13:52:18 -08:00
0882cc2715
Fix AXI4Tieoff missing import
2023-01-27 13:52:18 -08:00
3670816922
Bump scalafix
2023-01-27 13:52:18 -08:00
697b5a59d9
Remaining fixes to bump to scala 2.13
2023-01-27 13:52:18 -08:00
a560cd1b8e
Bump to scala 2.13/chisel 3.5.5
2023-01-27 13:52:18 -08:00
9c3cbf27d9
Merge pull request #1409 from firesim/fix-vitis-replace-rtl-cy-as-top
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Fix Vitis driver compilation + Fix CY-as-top driver builds
2023-01-27 12:53:39 -08:00
3151a7c391
Merge pull request #1414 from firesim/add-vitis-driver-build
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Add CI for Vitis driver outside of FPGA sims
2023-01-27 12:23:46 -08:00
2420807af6
Add CI for vitis driver
2023-01-27 10:16:20 -08:00
ad7d0f009e
Fix drivers
2023-01-27 18:00:48 +00:00
240875234d
Fix Vitis driver compile | Fix CY-as-top issues
2023-01-27 18:00:48 +00:00
f9b914d161
Merge pull request #1413 from caizixian/patch-1
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Use the new config filename in bitbuilder logging
2023-01-27 09:44:58 -08:00
bf6825e4fd
Use the new config filename in bitbuilder logging
2023-01-27 17:46:51 +11:00
Nandor Licker