From ff35d03dbba40ca61b027627baae148511582fbe Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Fri, 20 Mar 2020 23:46:25 +0000 Subject: [PATCH] Fix order of arguments to LogicNode in ClockSourceFinder --- sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala b/sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala index 2ca55c38..f54c9fdd 100644 --- a/sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala +++ b/sim/midas/src/main/scala/midas/passes/ClockSourceFinder.scala @@ -41,7 +41,8 @@ class ClockSourceFinder(state: CircuitState) { def findRootDriver(queryTarget: ReferenceTarget): Option[ReferenceTarget] = { require(queryTarget.component.isEmpty) def getPortDriver(rT: ReferenceTarget): Option[ReferenceTarget] = { - val node = LogicNode(rT.ref, rT.component.collectFirst { case Field(f) => f }) + val portOption = rT.component.collectFirst { case Field(f) => f } + val node = portOption.map(p => LogicNode(p, Some(rT.ref))).getOrElse(LogicNode(rT.ref)) val (inst, module) = rT.path.lastOption.getOrElse((Instance(rT.module), OfModule(rT.module))) val drivingCone = connectivity(module.value).reachableFrom(node) val drivingPorts = (drivingCone + node) & inputClockNodeSets(module.value)