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Merge remote-tracking branch 'origin/main' into cospike-integration

This commit is contained in:
abejgonzalez 2023-09-03 15:28:02 -07:00
parent 8339459c63 2691d8fa7c
commit f805350c27
2 changed files with 4 additions and 2 deletions
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2
sim/firesim-lib/src/main/cc/bridges/tracerv.cc
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@ -295,7 +295,7 @@ void tracerv_t::serialize(
// this stores as raw binary. stored as little endian.
// e.g. to get the same thing as the human readable above,
// flip all the bytes in each 512-bit line.
for (int q = 0; q < 8; q++) {
for (int q = 0; q < 1 + max_consider; q++) {
fwrite(OUTBUF + (i + q), sizeof(uint64_t), 1, tracefile);
}
}

4
sim/midas/src/main/scala/midas/widgets/FuzzingUIntSource.scala
View File

@ -23,7 +23,7 @@ class FuzzingUIntSourceBridge(width: Int) extends BlackBox
generateAnnotations()
}
class FuzzingUIntSourceBridgeModule(key: FuzzingUIntSourceKey)(implicit p: Parameters)
class FuzzingUIntSourceBridgeModule(key: FuzzingUIntSourceKey)(implicit p: Parameters)
extends BridgeModule[HostPortIO[FuzzingUIntSourceTargetIO]]()(p) {
lazy val module = new BridgeModuleImp(this) {
val io = IO(new WidgetIO())
@ -32,6 +32,8 @@ class FuzzingUIntSourceBridgeModule(key: FuzzingUIntSourceKey)(implicit p: Param
hPort.toHost.hReady := true.B
hPort.hBits.uint := chisel3.util.random.LFSR(key.width, hPort.fromHost.hReady)
io.ctrl := DontCare
override def genHeader(base: BigInt, memoryRegions: Map[String, BigInt], sb: StringBuilder): Unit = {}
}
}