From f6fe209f6ed4da555f5c66c1da5cf9d16b052509 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 28 May 2020 06:08:45 +0000 Subject: [PATCH] [WIP] Bloop support --- scripts/machine-launch-script.sh | 5 +++++ sim/.gitignore | 1 + sim/Makefile | 16 ++++++++++++++++ sim/project/plugins.sbt | 2 ++ sim/src/main/makefrag/fasedtests/Makefrag | 11 +++-------- sim/src/main/makefrag/midasexamples/Makefrag | 4 ++-- sim/target-agnostic.mk | 14 +++++++++++--- 7 files changed, 40 insertions(+), 13 deletions(-) diff --git a/scripts/machine-launch-script.sh b/scripts/machine-launch-script.sh index 000a1070..095a1575 100644 --- a/scripts/machine-launch-script.sh +++ b/scripts/machine-launch-script.sh @@ -47,6 +47,11 @@ sudo yum -y install graphviz python-devel # used for CI sudo yum -y install expect +# Optional: install bloop for fast scala builds on EC2 / CI +curl -fLo coursier https://git.io/coursier-cli-linux && +sudo cp coursier /usr/local/bin +coursier install bloop --only-prebuilt=true + # these need to match what's in deploy/requirements.txt sudo pip2 install fabric==1.14.0 sudo pip2 install boto3==1.6.2 diff --git a/sim/.gitignore b/sim/.gitignore index cc749c64..f220640f 100644 --- a/sim/.gitignore +++ b/sim/.gitignore @@ -8,3 +8,4 @@ AsyncResetReg.v firrtl_black_box_resource_files.f lib/firrtl.jar *.swp +.bloop/ diff --git a/sim/Makefile b/sim/Makefile index 34da8025..48c15813 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -34,10 +34,26 @@ base_dir := $(firesim_base_dir) chipyard_dir := $(abspath ..)/target-design/chipyard rocketchip_dir := $(chipyard_dir)/generators/rocket-chip +# Scala invocation options JVM_MEMORY ?= 16G SCALA_VERSION ?= 2.12.10 JAVA_ARGS ?= -Xmx$(JVM_MEMORY) SBT ?= java $(JAVA_ARGS) -jar $(rocketchip_dir)/sbt-launch.jar +BLOOP ?= bloop + +SCALA_BUILDTOOL_DEPS ?= build.sbt + +ifdef FIRESIM_USE_BLOOP +override SCALA_BUILDTOOL_DEPS += .bloop/TIMESTAMP +define run_scala_main + bloop run $(shell echo $(1) | sed 's/{.*}//') --main $(2) -- $(3) +endef +else +define run_scala_main + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" +endef +endif + # Manage the FIRRTL dependency manually FIRRTL_SUBMODULE_DIR ?= $(chipyard_dir)/tools/firrtl diff --git a/sim/project/plugins.sbt b/sim/project/plugins.sbt index a50f5bf1..6febe278 100644 --- a/sim/project/plugins.sbt +++ b/sim/project/plugins.sbt @@ -21,3 +21,5 @@ addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1") addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") + +addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1") diff --git a/sim/src/main/makefrag/fasedtests/Makefrag b/sim/src/main/makefrag/fasedtests/Makefrag index 8404dba2..6166080c 100644 --- a/sim/src/main/makefrag/fasedtests/Makefrag +++ b/sim/src/main/makefrag/fasedtests/Makefrag @@ -30,12 +30,7 @@ VERILOG := $(GENERATED_DIR)/FPGATop.v HEADER := $(GENERATED_DIR)/$(DESIGN)-const.h CONF_NAME ?= runtime.conf - -ifdef FIRESIM_STANDALONE - firesim_sbt_project := firesim -else - firesim_sbt_project := {file:${firesim_base_dir}/}firesim -endif +firesim_sbt_project := {file:${firesim_base_dir}/}firesim chisel_src_dirs = \ $(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \ $(addprefix $(chipyard_dir)/generators/, chipyard rocket-chip/src, rocket-chip/api-config-chipsalliance) @@ -45,11 +40,11 @@ chisel_srcs = $(foreach submodule,$(chisel_src_dirs),\ $(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR) mkdir -p $(@D) - cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain chipyard.Generator \ + $(call run_scala_main,$(firesim_sbt_project),chipyard.Generator, \ --target-dir $(GENERATED_DIR) \ --name $(long_name) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \ - --legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)" + --legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)) ########################## # Driver Sources & Flags # diff --git a/sim/src/main/makefrag/midasexamples/Makefrag b/sim/src/main/makefrag/midasexamples/Makefrag index 70ef138e..aaaf2c23 100644 --- a/sim/src/main/makefrag/midasexamples/Makefrag +++ b/sim/src/main/makefrag/midasexamples/Makefrag @@ -46,11 +46,11 @@ vcs_args = +vcs+initreg+0 +vcs+initmem+0 $(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR) mkdir -p $(@D) - cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain chipyard.Generator \ + $(call run_scala_main,$(firesim_sbt_project),chipyard.Generator, \ --target-dir $(GENERATED_DIR) \ --name $(long_name) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \ - --legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)" + --legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)) # Remove once runtime conf generation is generalized, and something is always emitted touch $(GENERATED_DIR)/$(CONF_NAME) diff --git a/sim/target-agnostic.mk b/sim/target-agnostic.mk index 80d7565a..50bd0033 100644 --- a/sim/target-agnostic.mk +++ b/sim/target-agnostic.mk @@ -52,13 +52,14 @@ firesim_root_sbt_project := {file:$(firesim_base_dir)}firesim # extracted used to generate new runtime configurations. fame_annos := $(GENERATED_DIR)/post-bridge-extraction.json -$(VERILOG) $(HEADER) $(fame_annos): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project $(midas_sbt_project)" "runMain midas.stage.GoldenGateMain \ +$(VERILOG) $(HEADER) $(fame_annos): $(FIRRTL_FILE) $(ANNO_FILE) $(SCALA_BUILDTOOL_DEPS) + $(call run_scala_main,$(firesim_sbt_project),midas.stage.GoldenGateMain,\ -o $(VERILOG) -i $(FIRRTL_FILE) -td $(GENERATED_DIR) \ -faf $(ANNO_FILE) \ -ggcp $(PLATFORM_CONFIG_PACKAGE) \ -ggcs $(PLATFORM_CONFIG) \ - -E verilog" + -E verilog \ + ) grep -sh ^ $(GENERATED_DIR)/firrtl_black_box_resource_files.f | \ xargs cat >> $(VERILOG) # Append blackboxes to FPGA wrapper, if any @@ -253,6 +254,13 @@ run-midas-unittests: $(chisel_srcs) run-midas-unittests-debug: $(chisel_srcs) $(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args) +######################### +# Bloop Project Defs # +######################### +.bloop/TIMESTAMP : build.sbt + cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "bloopInstall" + touch $@ + ######################### # ScalaDoc # #########################