[WIP] Bloop support
This commit is contained in:
David Biancolin
parent
5a1c4e727c
commit
f6fe209f6e
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@ -47,6 +47,11 @@ sudo yum -y install graphviz python-devel
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# used for CI
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sudo yum -y install expect
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# Optional: install bloop for fast scala builds on EC2 / CI
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curl -fLo coursier https://git.io/coursier-cli-linux &&
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sudo cp coursier /usr/local/bin
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coursier install bloop --only-prebuilt=true
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# these need to match what's in deploy/requirements.txt
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sudo pip2 install fabric==1.14.0
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sudo pip2 install boto3==1.6.2
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@ -8,3 +8,4 @@ AsyncResetReg.v
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firrtl_black_box_resource_files.f
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lib/firrtl.jar
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*.swp
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.bloop/
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16
sim/Makefile
16
sim/Makefile
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@ -34,10 +34,26 @@ base_dir := $(firesim_base_dir)
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chipyard_dir := $(abspath ..)/target-design/chipyard
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rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
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# Scala invocation options
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JVM_MEMORY ?= 16G
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SCALA_VERSION ?= 2.12.10
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JAVA_ARGS ?= -Xmx$(JVM_MEMORY)
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SBT ?= java $(JAVA_ARGS) -jar $(rocketchip_dir)/sbt-launch.jar
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BLOOP ?= bloop
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SCALA_BUILDTOOL_DEPS ?= build.sbt
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ifdef FIRESIM_USE_BLOOP
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override SCALA_BUILDTOOL_DEPS += .bloop/TIMESTAMP
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define run_scala_main
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bloop run $(shell echo $(1) | sed 's/{.*}//') --main $(2) -- $(3)
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endef
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else
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define run_scala_main
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cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
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endef
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endif
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# Manage the FIRRTL dependency manually
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FIRRTL_SUBMODULE_DIR ?= $(chipyard_dir)/tools/firrtl
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@ -21,3 +21,5 @@ addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
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addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
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addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")
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addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1")
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@ -30,12 +30,7 @@ VERILOG := $(GENERATED_DIR)/FPGATop.v
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HEADER := $(GENERATED_DIR)/$(DESIGN)-const.h
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CONF_NAME ?= runtime.conf
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ifdef FIRESIM_STANDALONE
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firesim_sbt_project := firesim
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else
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firesim_sbt_project := {file:${firesim_base_dir}/}firesim
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endif
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firesim_sbt_project := {file:${firesim_base_dir}/}firesim
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chisel_src_dirs = \
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$(addprefix $(firesim_base_dir)/,. midas midas/targetutils firesim-lib) \
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$(addprefix $(chipyard_dir)/generators/, chipyard rocket-chip/src, rocket-chip/api-config-chipsalliance)
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@ -45,11 +40,11 @@ chisel_srcs = $(foreach submodule,$(chisel_src_dirs),\
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$(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR)
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mkdir -p $(@D)
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cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain chipyard.Generator \
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$(call run_scala_main,$(firesim_sbt_project),chipyard.Generator, \
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--target-dir $(GENERATED_DIR) \
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--name $(long_name) \
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--top-module $(DESIGN_PACKAGE).$(DESIGN) \
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--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)"
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--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG))
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##########################
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# Driver Sources & Flags #
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@ -46,11 +46,11 @@ vcs_args = +vcs+initreg+0 +vcs+initmem+0
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$(FIRRTL_FILE) $(ANNO_FILE): $(chisel_srcs) $(FIRRTL_JAR)
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mkdir -p $(@D)
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cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "runMain chipyard.Generator \
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$(call run_scala_main,$(firesim_sbt_project),chipyard.Generator, \
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--target-dir $(GENERATED_DIR) \
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--name $(long_name) \
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--top-module $(DESIGN_PACKAGE).$(DESIGN) \
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--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG)"
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--legacy-configs $(TARGET_CONFIG_PACKAGE).$(TARGET_CONFIG))
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# Remove once runtime conf generation is generalized, and something is always emitted
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touch $(GENERATED_DIR)/$(CONF_NAME)
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@ -52,13 +52,14 @@ firesim_root_sbt_project := {file:$(firesim_base_dir)}firesim
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# extracted used to generate new runtime configurations.
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fame_annos := $(GENERATED_DIR)/post-bridge-extraction.json
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$(VERILOG) $(HEADER) $(fame_annos): $(FIRRTL_FILE) $(ANNO_FILE)
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cd $(base_dir) && $(SBT) "project $(midas_sbt_project)" "runMain midas.stage.GoldenGateMain \
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$(VERILOG) $(HEADER) $(fame_annos): $(FIRRTL_FILE) $(ANNO_FILE) $(SCALA_BUILDTOOL_DEPS)
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$(call run_scala_main,$(firesim_sbt_project),midas.stage.GoldenGateMain,\
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-o $(VERILOG) -i $(FIRRTL_FILE) -td $(GENERATED_DIR) \
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-faf $(ANNO_FILE) \
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-ggcp $(PLATFORM_CONFIG_PACKAGE) \
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-ggcs $(PLATFORM_CONFIG) \
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-E verilog"
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-E verilog \
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)
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grep -sh ^ $(GENERATED_DIR)/firrtl_black_box_resource_files.f | \
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xargs cat >> $(VERILOG) # Append blackboxes to FPGA wrapper, if any
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@ -253,6 +254,13 @@ run-midas-unittests: $(chisel_srcs)
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run-midas-unittests-debug: $(chisel_srcs)
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$(MAKE) -f $(simif_dir)/unittest/Makefrag $@ $(unittest_args)
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#########################
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# Bloop Project Defs #
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#########################
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.bloop/TIMESTAMP : build.sbt
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cd $(base_dir) && $(SBT) "project $(firesim_sbt_project)" "bloopInstall"
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touch $@
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#########################
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# ScalaDoc #
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#########################
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