[docs] Address remaining comments in #525 review
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@ -51,7 +51,7 @@ Runtime Arguments
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---------------------------
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**+print-file**
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Specifies the file name stem. Generated files will be of the form `<print-file><N>`,
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Specifies the file name prefix. Generated files will be of the form `<print-file><N>`,
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with one output file generated per clock domain. The associated clock
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domain's name and frequency relative to the base clock is included in the
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header of the output file.
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@ -26,7 +26,7 @@ Building a Design with TracerV
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In all FireChip designs, TracerV is included by default. Other targets can
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enable it by attaching a TracerV Bridge to the RISC-V trace port of each core
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they wish to trace (there should be one bridge per core). By default, only the
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cycle number, instruction address, and valid bit are pulled off the FPGA.
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cycle number, instruction address, and valid bit are collected.
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.. _tracerv-enabling:
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@ -154,7 +154,7 @@ Instruction value trigger
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Trace recording begins when a specific instruction is seen in the instruction
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trace and when a specific instruction is seen in the instruction
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trace and ends when a specific instruction is seen in the instruction
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trace. This method is particularly valuable for setting the trigger from
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within the target software under evaluation, by inserting custom "NOP"
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instructions. Linux distributions included with FireSim include small trigger
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@ -236,6 +236,15 @@ appearance in program order: ``I0`` is the oldest instruction committed, ``I1``
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is the second oldest, and so forth. If no instructions were committed in a
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given cycle, that cycle will be skipped in the output file.
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.. code-block:: ini
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Cycle: 0000000000000337 I0: 0000000000010010
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Cycle: 0000000000000337 I1: 0000000000010014
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|--------------| ^ |--------|
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| | └ 40 bits of instruction address (hex)
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| └ per-cycle commit-order
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└ 64-bit local-cycle count
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Binary output
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^^^^^^^^^^^^^^^^^
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@ -20,7 +20,9 @@ transformed and thus used in FireSim:
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#. Black boxes must be "clock-gateable" by replacing its input clock with a gated equivalent which will be used
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to stall simulation time in that module.
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#. As a consequence, target clock-gating cannot be implemented using black-box primitives, and must instead be modelled by
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adding clock-enables to all state elements of the gated clock domain.
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adding clock-enables to all state elements of the gated clock domain (i.e., by adding a feedback mux on registers to
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conditionally block updates, and by gating write-enables on memories).
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.
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#. Asynchronous reset must only be implemented using Rocket Chip's black-box async reset.
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These are replaced with synchronously reset registers using a FIRRTL transformation.
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