[docs] Address remaining comments in #525 review

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/Printf-Synthesis.rst

@@ -51,7 +51,7 @@ Runtime Arguments
 ---------------------------
 
 **+print-file**
-    Specifies the file name stem. Generated files will be of the form `<print-file><N>`,
+    Specifies the file name prefix. Generated files will be of the form `<print-file><N>`,
     with one output file generated per clock domain. The associated clock
     domain's name and frequency relative to the base clock is included in the
     header of the output file.

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TracerV.rst

@@ -26,7 +26,7 @@ Building a Design with TracerV
 In all FireChip designs, TracerV is included by default. Other targets can
 enable it by attaching a TracerV Bridge to the RISC-V trace port of each core
 they wish to trace (there should be one bridge per core).  By default, only the
-cycle number, instruction address, and valid bit are pulled off the FPGA.
+cycle number, instruction address, and valid bit are collected.
 
 .. _tracerv-enabling:
 
@@ -154,7 +154,7 @@ Instruction value trigger
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Trace recording begins when a specific instruction is seen in the instruction
-trace and  when a specific instruction is seen in the instruction
+trace and ends when a specific instruction is seen in the instruction
 trace. This method is particularly valuable for setting the trigger from
 within the target software under evaluation, by inserting custom "NOP"
 instructions. Linux distributions included with FireSim include small trigger
@@ -236,6 +236,15 @@ appearance in program order: ``I0`` is the oldest instruction committed, ``I1``
 is the second oldest, and so forth. If no instructions were committed in a
 given cycle, that cycle will be skipped in the output file.
 
+.. code-block:: ini
+
+    Cycle: 0000000000000337 I0: 0000000000010010
+    Cycle: 0000000000000337 I1: 0000000000010014
+           |--------------|  ^        |--------|
+                  |          |            └ 40 bits of instruction address (hex)
+                  |          └ per-cycle commit-order
+                  └ 64-bit local-cycle count
+
 Binary output
 ^^^^^^^^^^^^^^^^^
 

docs/Advanced-Usage/Generating-Different-Targets.rst

@@ -20,7 +20,9 @@ transformed and thus used in FireSim:
 #. Black boxes must be "clock-gateable" by replacing its input clock with a gated equivalent which will be used
    to stall simulation time in that module.
   #. As a consequence, target clock-gating cannot be implemented using black-box primitives, and must instead be modelled by
-     adding clock-enables to all state elements of the gated clock domain.
+     adding clock-enables to all state elements of the gated clock domain (i.e., by adding a feedback mux on registers to
+     conditionally block updates, and by gating write-enables on memories).
+     .
 #. Asynchronous reset must only be implemented using Rocket Chip's black-box async reset. 
    These are replaced with synchronously reset registers using a FIRRTL transformation.