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various cleanups

This commit is contained in:
Sagar Karandikar 2023-06-08 08:24:30 -07:00
parent 90ac53f2bb
commit f2388c2d52
3 changed files with 10 additions and 11 deletions
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6
deploy/sample-backup-configs/sample_config_build.yaml
View File

@ -39,15 +39,15 @@ builds_to_run:
# - firesim_gemmini_rocket_singlecore_no_nic
# - firesim_gemmini_printf_rocket_singlecore_no_nic
# Configs for vitis/xrt
# Configs for Vitis/XRT
# - vitis_firesim_rocket_singlecore_no_nic
# - vitis_firesim_gemmini_rocket_singlecore_no_nic
# Configs for Xilinx Alveo u250/u280
# Configs for Xilinx Alveo U250/U280
# - alveo_u250_firesim_rocket_singlecore_no_nic
# - alveo_u280_firesim_rocket_singlecore_no_nic
# Config for Xilinx vcu118
# Config for Xilinx VCU118
# - xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic
# Config for RHSResearch Nitefury II

4
docs/Advanced-Usage/Manager/HELP_OUTPUT generated
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@ -4,7 +4,7 @@ usage: firesim [-h] [-c RUNTIMECONFIGFILE] [-b BUILDCONFIGFILE]
[-g TERMINATESOMEF12] [-i TERMINATESOMEF14]
[-m TERMINATESOMEM416] [--terminatesome TERMINATESOME] [-q]
[-t LAUNCHTIME]
[--platform {f1,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}]
[--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}]
{managerinit,infrasetup,boot,kill,runworkload,buildbitstream,builddriver,enumeratefpgas,tar2afi,runcheck,launchrunfarm,terminaterunfarm,shareagfi}
FireSim Simulation Manager.
@ -76,6 +76,6 @@ options:
Give the "Y-m-d--H-M-S" prefix of results-build
directory. Useful for tar2afi when finishing a partial
buildbitstream
--platform {f1,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}
--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}
Required argument for "managerinit" to specify which
platform you will be using

11
sim/midas/src/main/cc/bridges/cpu_managed_stream.h
View File

@ -63,12 +63,10 @@ struct StreamParameters {
uint64_t dma_addr,
uint64_t count_addr,
int fpga_buffer_size,
int fpga_buffer_width_bytes
)
int fpga_buffer_width_bytes)
: stream_name(stream_name), dma_addr(dma_addr), count_addr(count_addr),
fpga_buffer_size(fpga_buffer_size),
fpga_buffer_width_bytes(fpga_buffer_width_bytes)
{}
fpga_buffer_width_bytes(fpga_buffer_width_bytes) {}
};
/**
@ -111,8 +109,9 @@ public:
int fpga_buffer_size() { return params.fpga_buffer_size; };
uint64_t dma_addr() { return params.dma_addr; };
uint64_t count_addr() { return params.count_addr; };
uint64_t fpga_buffer_width_bytes() const { return params.fpga_buffer_width_bytes; }
uint64_t fpga_buffer_width_bytes() const {
return params.fpga_buffer_width_bytes;
}
};
/**