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[midasexamples] Fix autocounter tests for naming plugin

This commit is contained in:
David Biancolin 2021-05-07 18:29:55 +00:00
parent 577b9666bf
commit e0b05a1304
2 changed files with 11 additions and 4 deletions
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11
sim/src/main/scala/midasexamples/AutoCounterModule.scala
View File

@ -11,12 +11,15 @@ import freechips.rocketchip.util.property._
class AutoCounterModuleDUT(
printfPrefix: String = "AUTOCOUNTER_PRINT ",
instPath: String = "AutoCounterModule_AutoCounterModuleDUT",
instName: String = "dut",
clockDivision: Int = 1) extends Module {
val io = IO(new Bundle {
val a = Input(Bool())
})
val instPath = s"${parentPathName}_${instName}"
suggestName(instName)
val enabled_cycles = RegInit(0.U(16.W))
when(io.a) { enabled_cycles := enabled_cycles + 1.U }
@ -87,6 +90,10 @@ class AutoCounterCoverModuleDUT extends Module {
val io = IO(new Bundle {
val a = Input(Bool())
})
val instName = "dut"
val instPath = s"${parentPathName}_${instName}"
suggestName(instName)
val cycle = RegInit(0.U(12.W))
cycle := cycle + 1.U
@ -108,7 +115,7 @@ class AutoCounterCoverModuleDUT extends Module {
when ((cycle_print >= (samplePeriod - 1).U) & (cycle_print % 1000.U === (samplePeriod - 1).U)) {
printf("AUTOCOUNTER_PRINT Cycle %d\n", cycle_print)
printf("AUTOCOUNTER_PRINT ============================\n")
printf("AUTOCOUNTER_PRINT PerfCounter CYCLES_DIV_8_AutoCounterCoverModule_AutoCounterCoverModuleDUT: %d\n", cycle8_printcount)
printf(s"AUTOCOUNTER_PRINT PerfCounter CYCLES_DIV_8_${instPath}: %d\n", cycle8_printcount)
printf("AUTOCOUNTER_PRINT \n")
}

4
sim/src/main/scala/midasexamples/MulticlockAutoCounterModule.scala
View File

@ -21,14 +21,14 @@ class MulticlockAutoCounterModule(implicit p: Parameters) extends RawModule {
val instPath = "MulticlockAutoCounterModule_AutoCounterModuleDUT"
withClockAndReset(refClock, reset) {
val lfsr = chisel3.util.random.LFSR(16)
val fullRateMod = Module(new AutoCounterModuleDUT(instPath = instPath))
val fullRateMod = Module(new AutoCounterModuleDUT(instName = "secondRate"))
fullRateMod.io.a := lfsr(0)
val peekPokeBridge = PeekPokeBridge(refClock, reset)
}
withClockAndReset(div2Clock, resetHalfRate) {
val lfsr = chisel3.util.random.LFSR(16)
val fullRateMod = Module(new AutoCounterModuleDUT("AUTOCOUNTER_PRINT_THIRDRATE ",
instPath = instPath + "_1",
instName = "thirdRate",
clockDivision = 3))
fullRateMod.io.a := lfsr(0)
}