replica
/
firesim
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert some files | Delete old files

This commit is contained in:
abejgonzalez 2023-05-12 21:28:27 -07:00
parent ee9ca40f50
commit d9afa05df9
5 changed files with 10 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sim/midas/src/main/cc/rtlsim/Makefrag-vcs
View File

@ -56,7 +56,7 @@ $(OUT_DIR)/$(DRIVER_NAME)-debug: $(vcs_v) $(vcs_cc) $(emul_h)
mkdir -p $(OUT_DIR)
rm -rf $(GEN_DIR)/$(DRIVER_NAME)-debug.csrc
rm -rf $(OUT_DIR)/$(DRIVER_NAME)-debug.daidir
$(VCS) $(vcs_rtl_flags) +define+FSDB +define+DEBUG -o $@ $(vcs_v) $(vcs_cc)
$(VCS) $(vcs_rtl_flags) +define+DEBUG -o $@ $(vcs_v) $(vcs_cc)
################################################################################
@ -83,4 +83,4 @@ $(OUT_DIR)/$(DRIVER_NAME)-post-synth-debug: $(vcs_v) $(vcs_cc) $(emul_h)
mkdir -p $(OUT_DIR)
rm -rf $(GEN_DIR)/$(DRIVER_NAME)-post-synth-debug.csrc
rm -rf $(OUT_DIR)/$(DRIVER_NAME)-post-synth-debug.daidir
$(VCS) $(vcs_post_synth_flags) +define+FSDB +define+DEBUG -o $@ $(vcs_v) $(vcs_cc)
$(VCS) $(vcs_post_synth_flags) +define+DEBUG -o $@ $(vcs_v) $(vcs_cc)

20
sim/midas/src/main/verilog/top.sv
View File

@ -141,41 +141,27 @@ module emul(
`ifndef VERILATOR
`ifdef DEBUG
reg [2047:0] waveformfile = 2048'h0;
reg [2047:0] vcdplusfile = 2048'h0;
reg [63:0] dump_start = 64'h0;
reg [63:0] dump_end = {64{1'b1}};
reg [63:0] dump_cycles = 64'h0;
reg [63:0] trace_count = 64'h0;
initial begin
if ($value$plusargs("waveform=%s", waveformfile))
if ($value$plusargs("waveform=%s", vcdplusfile))
begin
$value$plusargs("dump-start=%d", dump_start);
if ($value$plusargs("dump-cycles=%d", dump_cycles)) begin
dump_end = dump_start + dump_cycles;
end
`ifdef FSDB
$fsdbDumpfile(waveformfile);
$fsdbDumpvars("+all");
`else
$vcdplusfile(waveformfile);
`endif
$vcdplusfile(vcdplusfile);
wait (trace_count >= dump_start) begin
`ifdef FSDB
$fsdbDumpon;
`else
$vcdpluson(0);
$vcdplusmemon(0);
`endif
end
wait ((trace_count > dump_end) || fin) begin
`ifdef FSDB
$fsdbDumpoff;
`else
$vcdplusclose;
`endif
end
end
end

9
sim/runtest.sh
View File

@ -1,9 +0,0 @@
#!/usr/bin/env bash
RUNBIN=../target-design/chipyard/tests/blkdev.riscv
#RUNBIN=../riscv-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add
# generate a fresh test.stuff disk, all zeroed
dd if=/dev/zero bs=1M count=128 of=test.disk
./generated-src/f1/FireSimRocketConfig/FireSim +mm_readLatency=10 +mm_writeLatency=10 +mm_readMaxReqs=4 +mm_writeMaxReqs=4 +blkdev0=test.disk $RUNBIN

9
sim/src/main/makefrag/firesim/metasim.mk
View File

@ -59,7 +59,7 @@ run-vcs: $(vcs)
run-vcs-debug: $(vcs_debug)
cd $(dir $<) && \
$(vcs_debug) +permissive $(vcs_args) +waveform=$(sim_binary_basename).fsdb $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) </dev/null \
$(vcs_debug) +permissive $(vcs_args) +waveform=$(sim_binary_basename).vpd $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) +permissive-off $(abspath $(SIM_BINARY)) </dev/null \
$(disasm) $(sim_binary_basename).out </dev/null
.PHONY: run-xsim
@ -110,12 +110,7 @@ $(OUTPUT_DIR)/%.vpd: $(OUTPUT_DIR)/% $(EMUL)-debug
./$(notdir $($(EMUL)_debug)) $< +waveform=$@ $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \
$(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
$(OUTPUT_DIR)/%.fsdb: $(OUTPUT_DIR)/% $(EMUL)-debug
cd $(dir $($(EMUL)_debug)) && \
./$(notdir $($(EMUL)_debug)) $< +waveform=$@ $($*_ARGS) $($(EMUL)_args) $(COMMON_SIM_ARGS) $(MIDAS_LEVEL_SIM_ARGS) $(EXTRA_SIM_ARGS) \
$(disasm) $(patsubst %.fsdb,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
.PRECIOUS: $(OUTPUT_DIR)/%.fsdb $(OUTPUT_DIR)/%.vpd $(OUTPUT_DIR)/%.out $(OUTPUT_DIR)/%.run
.PRECIOUS: $(OUTPUT_DIR)/%.vpd $(OUTPUT_DIR)/%.out $(OUTPUT_DIR)/%.run
# TraceGen rules

12
sim/test.sh
View File

@ -1,12 +0,0 @@
#!/usr/bin/env bash
set -ex
make \
PLATFORM=xilinx_alveo_u250 \
TARGET_PROJECT=firesim \
DESIGN=FireSim \
TARGET_CONFIG=FireSimRocketConfig \
PLATFORM_CONFIG=BaseXilinxAlveoConfig \
SIM_BINARY=/scratch/abejgonza/firesim-private/sw/firesim-software/test/bare/hello \
clean