Merge pull request #765 from firesim/autocounter-ci

[ci] Add autocounter tests to CI

sim/src/main/scala/midasexamples/AutoCounterModule.scala

@@ -9,14 +9,28 @@ import chisel3.core.MultiIOModule
 import midas.targetutils.{PerfCounter, AutoCounterCoverModuleAnnotation}
 import freechips.rocketchip.util.property._
 
+/**
+  * Demonstrates how to instantiate autocounters, and validates those
+  * autocounter by comparing their output against a printf that should emit the
+  * same strings
+  *
+  * @param printfPrefix Used filter simulation output for validation lines
+  * @param instName The suggested name for this instance. Used in validation printf
+  * @param clockDivision Used to scale validation output, since autocounters in
+  *        slower domains will appear to be sampled less frequently (in terms of local
+  *        cycle count).
+  */
 class AutoCounterModuleDUT(
   printfPrefix: String = "AUTOCOUNTER_PRINT ",
-  instPath: String = "AutoCounterModule_AutoCounterModuleDUT",
+  instName: String = "dut",
   clockDivision: Int = 1) extends Module {
   val io = IO(new Bundle {
     val a = Input(Bool())
   })
 
+  val instPath = s"${parentPathName}_${instName}"
+  suggestName(instName)
+
   val enabled_cycles = RegInit(0.U(16.W))
 
   when(io.a) { enabled_cycles := enabled_cycles + 1.U }
@@ -87,6 +101,10 @@ class AutoCounterCoverModuleDUT extends Module {
   val io = IO(new Bundle {
     val a = Input(Bool())
   })
+  val instName = "dut"
+  val instPath = s"${parentPathName}_${instName}"
+  suggestName(instName)
+
 
   val cycle = RegInit(0.U(12.W))
   cycle := cycle + 1.U
@@ -108,7 +126,7 @@ class AutoCounterCoverModuleDUT extends Module {
   when ((cycle_print >= (samplePeriod - 1).U) & (cycle_print % 1000.U === (samplePeriod - 1).U)) {
     printf("AUTOCOUNTER_PRINT Cycle %d\n", cycle_print)
     printf("AUTOCOUNTER_PRINT ============================\n")
-    printf("AUTOCOUNTER_PRINT PerfCounter CYCLES_DIV_8_AutoCounterCoverModule_AutoCounterCoverModuleDUT: %d\n", cycle8_printcount)
+    printf(s"AUTOCOUNTER_PRINT PerfCounter CYCLES_DIV_8_${instPath}: %d\n", cycle8_printcount)
     printf("AUTOCOUNTER_PRINT \n")
   }
 

sim/src/main/scala/midasexamples/MulticlockAutoCounterModule.scala

@@ -21,14 +21,14 @@ class MulticlockAutoCounterModule(implicit p: Parameters) extends RawModule {
   val instPath = "MulticlockAutoCounterModule_AutoCounterModuleDUT"
   withClockAndReset(refClock, reset) {
     val lfsr = chisel3.util.random.LFSR(16)
-    val fullRateMod = Module(new AutoCounterModuleDUT(instPath = instPath))
+    val fullRateMod = Module(new AutoCounterModuleDUT(instName = "secondRate"))
     fullRateMod.io.a := lfsr(0)
     val peekPokeBridge = PeekPokeBridge(refClock, reset)
   }
   withClockAndReset(div2Clock, resetHalfRate) {
     val lfsr = chisel3.util.random.LFSR(16)
     val fullRateMod = Module(new AutoCounterModuleDUT("AUTOCOUNTER_PRINT_THIRDRATE ",
-                                                      instPath = instPath + "_1",
+                                                      instName = "thirdRate",
                                                       clockDivision = 3))
     fullRateMod.io.a := lfsr(0)
   }

sim/src/test/scala/midasexamples/TutorialSuite.scala

@@ -305,6 +305,7 @@ class CIGroupA extends Suites(
   new ChiselExampleDesigns,
   new PrintfSynthesisCITests,
   new firesim.fasedtests.CIGroupA,
+  new AutoCounterCITests
 )
 
 class CIGroupB extends Suites(