Resolve some common spelling mistakes (#1186)

CHANGELOG.md

@@ -168,7 +168,7 @@ FIRRTL deduplication interaction.
 * Fix VCS-related breakages in MIDASExamples, SynthUnittests #725
 * Fix breakages related to new FIRRTL 1.4 DedupModules by limiting how many times it runs (#738, see #766)
 * Replace DualQueue in the DRAM memory model scheduler with RRArbiter+Queue to prevent write starvation (#753)
-* A bug that broke tracerV when using heterogenous mixes of tiles #776 
+* A bug that broke tracerV when using heterogeneous mixes of tiles #776
 
 ### Removed
 * Coremark and SPEC workloads moved to Chipyard
@@ -492,7 +492,7 @@ A more detailed account of everything included is included in the dev->master PR
     * Resolves #56 
 * PR #193. Fedora networking now works in FireSim 
     * Address assignment fixed (gets assigned IP addresses in slot-order on firesim)
-* PR #204. Fix support for heterogenous rootfs's - each job can have its own rootfs, or no rootfs at all
+* PR #204. Fix support for heterogeneous rootfs's - each job can have its own rootfs, or no rootfs at all
 
 ### Deprecated
 

deploy/runtools/utils.py

@@ -28,7 +28,7 @@ def get_local_shared_libraries(elf: str) -> List[Tuple[str, str]]:
          * known members of glibc.  These could be copyable but
            glibc is very coupled to the kernel version and following the pattern
            of the conda packages we build from, we will not copy glibc around.
-           We compile against centos7 glibc and given the backwards compatability of glibc
+           We compile against centos7 glibc and given the backwards compatibility of glibc
            should be able to copy everything else to most other hosts
            and they will work from a DSO linker/loader perspective (i.e.
            if you're building a driver for AWS, it doesn't magically work

platforms/vitis/cl_firesim/Makefile

@@ -142,7 +142,7 @@ $(SIM_RUN_DIR)/emconfig.json:
 	emconfigutil --platform $(DEVICE) --od $(SIM_RUN_DIR)
 
 # Populate the run directory. Vitis wants certain files to reside in the same
-# directory as the application binary, keep things seperated by building up a
+# directory as the application binary, keep things separated by building up a
 # fresh location that can be cleanly removed.
 delivered_sim_inputs = $(addprefix $(SIM_RUN_DIR)/, $(driver_bin) $(runtime_conf))
 $(SIM_RUN_DIR)/%: $(DRIVER_DIR)/%

sim/midas/README.md

@@ -30,7 +30,7 @@ but other resource-reducing optimizations are under development.
 ### 2. Different Inputs and Invocation Model (FIRRTL Stage).
 
 Golden Gate is not invoked in the same process as the target generator.
-instead it's invoked as a seperate process and provided with three inputs:
+instead it's invoked as a separate process and provided with three inputs:
 1) FIRRTL for the target-design
 2) Associated FIRRTL annotations for that design
 3) A compiler parameterization (derived from Rocket Chip's Config system).

sim/midas/src/main/cc/rtlsim/ml-verilator-conf.vlt

@@ -1,5 +1,5 @@
 // HACK: Disable MULTIDRIVEN linting, since verilator cannot determine if two
 // syntactically different clocks are aliases of one another if they are
-// driven by seperate ports.
+// driven by separate ports.
 `verilator_config
 lint_off -rule MULTIDRIVEN

sim/midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala

@@ -10,7 +10,7 @@ import firrtl.ir._
 import firrtl.options.Dependency
 
 /**
-  * Pushes enable expressions into seperate nodes that can be consistently
+  * Pushes enable expressions into separate nodes that can be consistently
   * optimized across by CSE. This ensures that associated pairs of stops and
   * printfs will have references to a common enable node, which allows
   * AssertionSynthesis to correctly group and synthesize them.

sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala

@@ -69,7 +69,7 @@ class GoldenGateCompilerPhase extends Phase {
     val loweredSimulator = hostLoweringCompiler.execute(simulator)
 
     // Workaround under-constrained transform dependencies by forcing the
-    // emitter to run last in a seperate compiler.
+    // emitter to run last in a separate compiler.
     val emitter = new Compiler(
         Seq(Dependency(midas.passes.WriteXDCFile), Dependency[firrtl.SystemVerilogEmitter]),
         Forms.LowForm)

sim/midas/src/main/scala/midas/widgets/HostPort.scala

@@ -84,7 +84,7 @@ class HostPortIO[+T <: Data](private val targetPortProto: T) extends Record with
             leafTargets
           )
         } else {
-        // Bridge is the source; it asserts target-valid and recieves target-backpressure
+        // Bridge is the source; it asserts target-valid and receives target-backpressure
           FAMEChannelConnectionAnnotation.sink(
             fwdChName,
             DecoupledForwardChannel.sink(validTarget, readyTarget),