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[midaseamples] Fix a reset elaboration bug in VerilogAccumulator (#773)

This commit is contained in:
David Biancolin 2021-06-03 17:14:40 -07:00 committed by GitHub
parent dd54294f12
commit cf992acf8c
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 6 additions and 2 deletions
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2
sim/src/main/scala/midasexamples/VerilogAccumulator.scala
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@ -49,7 +49,7 @@ class VerilogAccumulatorDUT extends Module {
val io = IO(new AccumulatorIO)
val impl = Module(new VerilogAccumulatorImpl)
impl.io.clock := clock
impl.io.reset := reset
impl.io.reset := reset.asBool
impl.io.in := io.in
io.out := impl.io.out
}

6
sim/src/test/scala/midasexamples/TutorialSuite.scala
View File

@ -141,6 +141,8 @@ class EnableShiftRegisterF1Test extends TutorialSuite("EnableShiftRegister")
class StackF1Test extends TutorialSuite("Stack")
class RiscF1Test extends TutorialSuite("Risc")
class RiscSRAMF1Test extends TutorialSuite("RiscSRAM")
class AccumulatorF1Test extends TutorialSuite("Accumulator")
class VerilogAccumulatorF1Test extends TutorialSuite("VerilogAccumulator")
class AssertModuleF1Test extends TutorialSuite("AssertModule")
class AutoCounterModuleF1Test extends TutorialSuite("AutoCounterModule",
simulationArgs = Seq("+autocounter-readrate=1000", "+autocounter-filename=AUTOCOUNTERFILE")) {
@ -267,7 +269,9 @@ class ChiselExampleDesigns extends Suites(
new EnableShiftRegisterF1Test,
new StackF1Test,
new RiscF1Test,
new RiscSRAMF1Test
new RiscSRAMF1Test,
new AccumulatorF1Test,
new VerilogAccumulatorF1Test
)
class PrintfSynthesisCITests extends Suites(