The finest bugfix in my time at Berkeley
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@ -7,7 +7,7 @@ module BUFGCE(
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always @(posedge I)
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always @(posedge I)
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enable_latch <= CE;
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enable_latch <= CE;
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`ifdef VERILATOR
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`ifdef VERILATOR
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// Verilator doesn't like procedural clock gates
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// Note: Verilator doesn't like procedural clock gates
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// They cause combinational loop errors and UNOPT_FLAT
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// They cause combinational loop errors and UNOPT_FLAT
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assign O = (I & enable_latch);
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assign O = (I & enable_latch);
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`else
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`else
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