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Change top-level io | Don't exit immediately

This commit is contained in:
abejgonzalez 2021-10-22 15:24:00 -07:00
parent 8f1b2a4de1
commit c7c514be9a
2 changed files with 20 additions and 20 deletions
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12
sim/midas/src/main/cc/simif_vitis.cc
View File

@ -55,8 +55,8 @@ void simif_vitis_t::write(size_t addr, uint32_t data) {
addr <<= CTRL_AXI4_SIZE;
kernel_handle.write_register(addr, data);
fprintf(stdout, "DEBUG: Write 0x%lx:%d\n", addr, data);
exit(1);
fprintf(stdout, "DEBUG: Write 0x%lx(%ld):%d\n", addr, addr/4, data);
//exit(1);
}
uint32_t simif_vitis_t::read(size_t addr) {
@ -65,8 +65,8 @@ uint32_t simif_vitis_t::read(size_t addr) {
uint32_t value;
value = kernel_handle.read_register(addr);
fprintf(stdout, "DEBUG: Read 0x%lx:%d\n", addr, value);
exit(1);
fprintf(stdout, "DEBUG: Read 0x%lx(%ld):%d\n", addr, addr/4, value);
//exit(1);
return value & 0xFFFFFFFF;
}
@ -86,8 +86,8 @@ uint32_t simif_vitis_t::is_write_ready() {
uint32_t value;
value = kernel_handle.read_register(addr);
fprintf(stdout, "DEBUG: Read-is_write_ready() 0x%lx:%d\n", addr, value);
exit(1);
fprintf(stdout, "DEBUG: Read-is_write_ready() 0x%lx(%ld):%d\n", addr, addr/4, value);
//exit(1);
return value & 0xFFFFFFFF;
}

28
sim/midas/src/main/scala/midas/platform/VitisShim.scala
View File

@ -16,9 +16,9 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle{
val master = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(CtrlNastiKey) })))
val dma = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(DMANastiKey) })))
//val dma = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(DMANastiKey) })))
})
val io_slave = IO(HeterogeneousBag(top.module.mem.map(x => x.cloneType)))
//val io_slave = IO(HeterogeneousBag(top.module.mem.map(x => x.cloneType)))
top.module.ctrl <> io.master
//top.module.dma <> io.dma
@ -31,11 +31,11 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
top.module.dma.r.ready := false.B
top.module.dma.b.ready := false.B
io.dma.ar.ready := false.B
io.dma.aw.ready := false.B
io.dma.w.ready := false.B
io.dma.r.valid := false.B
io.dma.b.valid := false.B
//io.dma.ar.ready := false.B
//io.dma.aw.ready := false.B
//io.dma.w.ready := false.B
//io.dma.r.valid := false.B
//io.dma.b.valid := false.B
top.module.mem.foreach({ case bundle =>
bundle.ar.ready := false.B
@ -45,13 +45,13 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
bundle.b.valid := false.B
})
io_slave.foreach({ case bundle =>
bundle.ar.valid := false.B
bundle.aw.valid := false.B
bundle.w.valid := false.B
bundle.r.ready := false.B
bundle.b.ready := false.B
})
//io_slave.foreach({ case bundle =>
// bundle.ar.valid := false.B
// bundle.aw.valid := false.B
// bundle.w.valid := false.B
// bundle.r.ready := false.B
// bundle.b.ready := false.B
//})
// Biancolin: It would be good to put in writing why ID is being reassigned...
val (wCounterValue, wCounterWrap) = Counter(io.master.aw.fire(), 1 << p(CtrlNastiKey).idBits)