Change top-level io | Don't exit immediately
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8f1b2a4de1
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@ -55,8 +55,8 @@ void simif_vitis_t::write(size_t addr, uint32_t data) {
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addr <<= CTRL_AXI4_SIZE;
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kernel_handle.write_register(addr, data);
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fprintf(stdout, "DEBUG: Write 0x%lx:%d\n", addr, data);
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exit(1);
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fprintf(stdout, "DEBUG: Write 0x%lx(%ld):%d\n", addr, addr/4, data);
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//exit(1);
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}
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uint32_t simif_vitis_t::read(size_t addr) {
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@ -65,8 +65,8 @@ uint32_t simif_vitis_t::read(size_t addr) {
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uint32_t value;
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value = kernel_handle.read_register(addr);
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fprintf(stdout, "DEBUG: Read 0x%lx:%d\n", addr, value);
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exit(1);
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fprintf(stdout, "DEBUG: Read 0x%lx(%ld):%d\n", addr, addr/4, value);
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//exit(1);
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return value & 0xFFFFFFFF;
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}
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@ -86,8 +86,8 @@ uint32_t simif_vitis_t::is_write_ready() {
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uint32_t value;
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value = kernel_handle.read_register(addr);
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fprintf(stdout, "DEBUG: Read-is_write_ready() 0x%lx:%d\n", addr, value);
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exit(1);
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fprintf(stdout, "DEBUG: Read-is_write_ready() 0x%lx(%ld):%d\n", addr, addr/4, value);
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//exit(1);
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return value & 0xFFFFFFFF;
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}
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@ -16,9 +16,9 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle{
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val master = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(CtrlNastiKey) })))
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val dma = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(DMANastiKey) })))
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//val dma = Flipped(new NastiIO()(p alterPartial ({ case NastiKey => p(DMANastiKey) })))
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})
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val io_slave = IO(HeterogeneousBag(top.module.mem.map(x => x.cloneType)))
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//val io_slave = IO(HeterogeneousBag(top.module.mem.map(x => x.cloneType)))
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top.module.ctrl <> io.master
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//top.module.dma <> io.dma
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@ -31,11 +31,11 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
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top.module.dma.r.ready := false.B
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top.module.dma.b.ready := false.B
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io.dma.ar.ready := false.B
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io.dma.aw.ready := false.B
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io.dma.w.ready := false.B
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io.dma.r.valid := false.B
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io.dma.b.valid := false.B
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//io.dma.ar.ready := false.B
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//io.dma.aw.ready := false.B
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//io.dma.w.ready := false.B
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//io.dma.r.valid := false.B
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//io.dma.b.valid := false.B
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top.module.mem.foreach({ case bundle =>
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bundle.ar.ready := false.B
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@ -45,13 +45,13 @@ class VitisShim(implicit p: Parameters) extends PlatformShim {
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bundle.b.valid := false.B
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})
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io_slave.foreach({ case bundle =>
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bundle.ar.valid := false.B
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bundle.aw.valid := false.B
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bundle.w.valid := false.B
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bundle.r.ready := false.B
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bundle.b.ready := false.B
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})
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//io_slave.foreach({ case bundle =>
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// bundle.ar.valid := false.B
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// bundle.aw.valid := false.B
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// bundle.w.valid := false.B
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// bundle.r.ready := false.B
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// bundle.b.ready := false.B
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//})
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// Biancolin: It would be good to put in writing why ID is being reassigned...
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val (wCounterValue, wCounterWrap) = Counter(io.master.aw.fire(), 1 << p(CtrlNastiKey).idBits)
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