non-submodule changes for RC bump

sim/Makefile

@@ -18,7 +18,7 @@ TARGET_PROJECT_MAKEFRAG ?= src/main/makefrag/$(TARGET_PROJECT)/Makefrag
 default: compile
 
 SBT ?= sbt
-SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=512M -J-XX:ReservedCodeCacheSize=1G
+SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=512M -J-XX:ReservedCodeCacheSize=1G ++2.12.4
 sbt:
 	$(SBT) $(SBT_FLAGS)
 test:

sim/build.sbt

@@ -1,9 +1,9 @@
 lazy val commonSettings = Seq(
   organization := "berkeley",
   version      := "1.0",
-  scalaVersion := "2.11.12",
+  scalaVersion := "2.12.4",
   traceLevel   := 15,
-  scalacOptions ++= Seq("-deprecation","-unchecked"),
+  scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
   libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test",
   libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3",
   libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
@@ -15,7 +15,7 @@ lazy val commonSettings = Seq(
 )
 
 lazy val rocketchip = RootProject(file("target-rtl/firechip/rocket-chip"))
-lazy val boom       = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
+//lazy val boom       = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
 lazy val sifiveip   = project in file("target-rtl/firechip/sifive-blocks") settings commonSettings dependsOn rocketchip
 lazy val testchipip = project in file("target-rtl/firechip/testchipip") settings commonSettings dependsOn rocketchip
 lazy val icenet     = project in file("target-rtl/firechip/icenet") settings commonSettings dependsOn (rocketchip, testchipip)
@@ -24,4 +24,4 @@ lazy val mdf        = RootProject(file("barstools/mdf/scalalib"))
 lazy val barstools  = project in file("barstools/macros") settings commonSettings dependsOn (mdf, rocketchip)
 lazy val midas      = project in file("midas") settings commonSettings dependsOn barstools
 
-lazy val firesim    = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet, boom)
+lazy val firesim    = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet/*, boom*/)

sim/src/main/scala/endpoints/UARTWidget.scala

@@ -19,7 +19,7 @@ class SimUART extends Endpoint {
   }
   def widget(p: Parameters) = {
     val frequency = p(PeripheryBusKey).frequency
-    val baudrate = p(PeripheryUARTKey).head.initBaudRate
+    val baudrate = 115200L
     val div = (p(PeripheryBusKey).frequency / baudrate).toInt
     new UARTWidget(div)(p)
   }

sim/src/main/scala/firesim/Generator.scala

@@ -14,7 +14,7 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.subsystem.RocketTilesKey
 import freechips.rocketchip.tile.XLen
 
-import boom.system.{BoomTilesKey, BoomTestSuites}
+/*import boom.system.{BoomTilesKey, BoomTestSuites}*/
 
 case class FireSimGeneratorArgs(
   midasFlowKind: String = "midas", // "midas", "strober", "replay"
@@ -61,9 +61,9 @@ trait HasFireSimGeneratorUtilities extends HasGeneratorUtilities with HasTestSui
     implicit val valName = ValName(targetNames.topModuleClass)
     targetNames.topModuleClass match {
       case "FireSim"  => LazyModule(new FireSim()(params)).module
-      case "FireBoom" => LazyModule(new FireBoom()(params)).module
+//      case "FireBoom" => LazyModule(new FireBoom()(params)).module
       case "FireSimNoNIC"  => LazyModule(new FireSimNoNIC()(params)).module
-      case "FireBoomNoNIC" => LazyModule(new FireBoomNoNIC()(params)).module
+//      case "FireBoomNoNIC" => LazyModule(new FireBoomNoNIC()(params)).module
     }
   }
 
@@ -163,11 +163,11 @@ trait HasTestSuites {
 
   def addTestSuites(params: Parameters) {
     val coreParams =
-      if (params(RocketTilesKey).nonEmpty) {
+//      if (params(RocketTilesKey).nonEmpty) {
         params(RocketTilesKey).head.core
-      } else {
-        params(BoomTilesKey).head.core
-      }
+//      } else {
+//        params(BoomTilesKey).head.core
+//      }
     val xlen = params(XLen)
     val vm = coreParams.useVM
     val env = if (vm) List("p","v") else List("p")
@@ -186,8 +186,8 @@ trait HasTestSuites {
     if (coreParams.useAtomics)    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
     if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
     val (rvi, rvu) =
-      if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
-      else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+/*      if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
+      else */if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
       else            ((if (vm) rv32i else rv32pi), rv32u)
 
     TestGeneration.addSuites(rvi.map(_("p")))

sim/src/main/scala/firesim/TargetConfigs.scala

@@ -5,7 +5,7 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
-import boom.system.BoomTilesKey
+/*import boom.system.BoomTilesKey*/
 import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import icenet._
@@ -21,8 +21,8 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
 
 class WithUARTKey extends Config((site, here, up) => {
    case PeripheryUARTKey => List(UARTParams(
-     address = BigInt(0x54000000L),
-     initBaudRate = BigInt(3686400L)))
+     address = BigInt(0x54000000L) /*,
+     initBaudRate = BigInt(3686400L)*/))
 })
 
 class WithNICKey extends Config((site, here, up) => {
@@ -49,14 +49,14 @@ class WithPerfCounters extends Config((site, here, up) => {
   ))
 })
 
-class BoomWithLargeTLBs extends Config((site, here, up) => {
+/*class BoomWithLargeTLBs extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
     core = tile.core.copy(
       nL2TLBEntries = 1024 // TLB reach = 1024 * 4KB = 4MB
     )
   ))
 })
-
+*/
 
 /*******************************************************************************
 * Full TARGET_CONFIG configurations. These set parameters of the target being
@@ -99,7 +99,7 @@ class FireSimRocketChipHexaCoreConfig extends Config(new WithNBigCores(6) ++
 class FireSimRocketChipOctaCoreConfig extends Config(new WithNBigCores(8) ++
   new FireSimRocketChipSingleCoreConfig)
 
-
+/*
 class FireSimBoomConfig extends Config(
   new WithBootROM ++
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
@@ -110,4 +110,4 @@ class FireSimBoomConfig extends Config(
   new WithBlockDevice ++
   new BoomWithLargeTLBs ++
   // Using a small config because it has 64-bit system bus, and compiles quickly
-  new boom.system.SmallBoomConfig)
+  new boom.system.SmallBoomConfig)*/

sim/src/main/scala/firesim/Targets.scala

@@ -4,7 +4,7 @@ import freechips.rocketchip._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.config.Parameters
-import boom.system.{BoomSubsystem, BoomSubsystemModule}
+/*import boom.system.{BoomSubsystem, BoomSubsystemModule}*/
 import icenet._
 import testchipip._
 import sifive.blocks.devices.uart._
@@ -71,7 +71,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
     with HasPeripheryBlockDeviceModuleImp
 
 
-
+/*
 class FireBoom(implicit p: Parameters) extends BoomSubsystem
     with CanHaveMisalignedMasterAXI4MemPort
     with HasPeripheryBootROM
@@ -119,3 +119,4 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemMod
     with HasPeripherySerialModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
+    */

target-design/TODO

@@ -0,0 +1,3 @@
+-have not bumped riscv-tools
+-have not fixed boom
+-probably want to bump linux too