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[MIDAS] fix things for the new Chisel

This commit is contained in:
Donggyu Kim 2014-09-22 20:00:27 -07:00
parent da34ad0932
commit bbf8f23e73
2 changed files with 5 additions and 16 deletions
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2
chisel

@ -1 +1 @@
Subproject commit f85a5f9c180a7ce1db29e23e8a1be41e6acb454c Subproject commit ec8190095ee6121861d22103c75511f6590f5789

19
src/main/scala/DaisyBackend.scala
View File

@ -27,26 +27,15 @@ object DaisyBackend {
Driver.backend.transforms += addSnapshotChains Driver.backend.transforms += addSnapshotChains
} }
def addPin[T <: Data](m: Module, pin: T, name: String) = {
for ((n, io) <- pin.flatten) {
io.component = m
io.isIo = true
}
if (name != "")
pin nameIt (name, true)
m.io.asInstanceOf[Bundle] += pin
pin
}
def addDaisyPins(c: Module) { def addDaisyPins(c: Module) {
ChiselError.info("[DaisyBackend] add daisy pins") ChiselError.info("[DaisyBackend] add daisy pins")
for (m <- Driver.sortedComps) { for (m <- Driver.sortedComps) {
if (m.name == top.name) { if (m.name == top.name) {
firePins(m) = top.stepCounter.orR firePins(m) = top.stepCounter.orR
} else { } else {
firePins(m) = addPin(m, Bool(INPUT), "fire") firePins(m) = m.addPin(Bool(INPUT), "fire")
regsIns(m) = addPin(m, Valid(UInt(width=daisywidth)).flip, "regs_in") regsIns(m) = m.addPin(Valid(UInt(width=daisywidth)).flip, "regs_in")
regsOuts(m) = addPin(m, Decoupled(UInt(width=daisywidth)), "regs_out") regsOuts(m) = m.addPin(Decoupled(UInt(width=daisywidth)), "regs_out")
} }
} }
} }
@ -119,7 +108,7 @@ object DaisyBackend {
} }
} else { } else {
val datawidth = (elems foldLeft 0)(_ + _.needWidth()) val datawidth = (elems foldLeft 0)(_ + _.needWidth())
val chain = Module(new RegChain(datawidth), m) val chain = m.addModule(new RegChain(datawidth))
chains += chain chains += chain
chain.io.dataIn := UInt(Concatenate(elems)) chain.io.dataIn := UInt(Concatenate(elems))
chain.io.stall := !firePins(m) chain.io.stall := !firePins(m)