Merge pull request #780 from firesim/bump_chisel3_new
Resolve Chisel Deprecations
This commit is contained in:
commit
bbf1acd741
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@ -78,10 +78,10 @@ class BlockDevBridgeModule(blockDevExternal: BlockDeviceConfig, hostP: Parameter
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// Decoupled helper can't exclude two bools unfortunately...
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val targetReset = channelCtrlSignals.reduce(_ && _) && hPort.hBits.reset
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reqBuf.reset := reset.toBool || targetReset
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dataBuf.reset := reset.toBool || targetReset
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rRespBuf.reset := reset.toBool || targetReset
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wAckBuf.reset := reset.toBool || targetReset
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reqBuf.reset := reset.asBool || targetReset
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dataBuf.reset := reset.asBool || targetReset
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rRespBuf.reset := reset.asBool || targetReset
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wAckBuf.reset := reset.asBool || targetReset
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hPort.toHost.hReady := tFireHelper.fire
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hPort.fromHost.hValid := tFireHelper.fire
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@ -104,7 +104,7 @@ class BlockDevBridgeModule(blockDevExternal: BlockDeviceConfig, hostP: Parameter
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val readLatency = genWORegInit(Wire(UInt(latencyBits.W)), "read_latency", defaultReadLatency)
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val writeLatency = genWORegInit(Wire(UInt(latencyBits.W)), "write_latency", defaultWriteLatency)
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withReset(reset.toBool || targetReset) {
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withReset(reset.asBool || targetReset) {
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when (tFire) {
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assert(!target.req.fire || ((dataBeats.U * target.req.bits.len) < ((BigInt(1) << sectorBits) - 1).U),
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"Transaction length exceeds timing model maximum supported length")
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@ -56,8 +56,8 @@ class SerialBridgeModule(serialBridgeParams: SerialBridgeParams)(implicit p: Par
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val target = hPort.hBits.serial
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val tFire = hPort.toHost.hValid && hPort.fromHost.hReady && tokensToEnqueue =/= 0.U
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val targetReset = tFire & hPort.hBits.reset
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inBuf.reset := reset.toBool || targetReset
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outBuf.reset := reset.toBool || targetReset
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inBuf.reset := reset.asBool || targetReset
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outBuf.reset := reset.asBool || targetReset
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hPort.toHost.hReady := tFire
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hPort.fromHost.hValid := tFire
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@ -101,8 +101,8 @@ class UARTBridgeModule(key: UARTKey)(implicit p: Parameters) extends BridgeModul
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hPort.fromHost.hReady && // We have space to enqueue a new output token
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txfifo.io.enq.ready // We have space to capture new TX data
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val targetReset = fire & hPort.hBits.reset
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rxfifo.reset := reset.toBool || targetReset
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txfifo.reset := reset.toBool || targetReset
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rxfifo.reset := reset.asBool || targetReset
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txfifo.reset := reset.asBool || targetReset
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hPort.toHost.hReady := fire
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hPort.fromHost.hValid := fire
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@ -34,7 +34,7 @@ object AsyncResetRegPass extends firrtl.Transform {
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def renameClockReset(s: Statement): Statement =
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s map renameClockResetExp map renameClockReset
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private val chirrtl = Parser.parse(chisel3.Driver.emit(() => new AsyncResetReg))
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private val chirrtl = chisel3.stage.ChiselStage.convert(new AsyncResetReg)
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private val circuit = (new MiddleFirrtlCompiler).compile(
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CircuitState(chirrtl, ChirrtlForm), Nil).circuit
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private val module = (circuit.modules collect {
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@ -35,41 +35,3 @@ class Midas2QoRTargets extends Config((site, here, up) => {
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}
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})
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// Generates synthesizable unit tests for key modules, such as simulation channels
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// See: src/main/cc/unittest/Makefile for the downstream RTL-simulation flow
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//
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// TODO: Make the core of this generator a trait that can be mixed into
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// FireSim's ScalaTests for more type safety
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object QoRShimGenerator extends App with midas.rocketchip.util.HasGeneratorUtilities {
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case class QoRShimOptions(
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configProject: String = "midas.unittest",
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config: String = "Midas2QoRTargets") {
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val fullConfigClasses: Seq[String] = Seq(configProject + "." + config)
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}
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trait HasUnitTestOptions {
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self: ExecutionOptionsManager =>
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var qorOptions = QoRShimOptions()
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parser.note("MIDAS Unit Test Generator Options")
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parser.opt[String]("config-project")
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.abbr("cp")
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.valueName("<config-project>")
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.foreach { d => qorOptions = qorOptions.copy(configProject = d) }
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parser.opt[String]("config")
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.abbr("conf")
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.valueName("<configClassName>")
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.foreach { cfg => qorOptions = qorOptions.copy(config = cfg) }
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}
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val exOptions = new ExecutionOptionsManager("qor")
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with HasChiselExecutionOptions
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with HasFirrtlOptions
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with HasUnitTestOptions
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exOptions.parse(args)
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val params = getConfig(exOptions.qorOptions.fullConfigClasses).toInstance
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Driver.execute(exOptions, () => new QoRShim()(params))
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}
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@ -37,7 +37,7 @@ class PipeChannel[T <: ChLeafType](
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io.out <> tokens.io.deq
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if (latency == 1) {
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val initializing = RegNext(reset.toBool)
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val initializing = RegNext(reset.asBool)
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when(initializing) {
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tokens.io.enq.valid := true.B
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tokens.io.enq.bits := 0.U.asTypeOf(tokens.io.enq.bits)
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@ -213,7 +213,7 @@ class ReadyValidChannel[T <: Data](
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enqFwdQ.io.deq.ready := finishing.fire(enqFwdQ.io.deq.valid)
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deqRevQ.io.deq.ready := finishing.fire(deqRevQ.io.deq.valid)
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reference.reset := reset.toBool || targetFire && io.targetReset.bits
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reference.reset := reset.asBool || targetFire && io.targetReset.bits
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reference.io.enq.valid := targetFire && enqFwdQ.io.deq.bits.valid
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reference.io.enq.bits := Mux(targetFire, enqFwdQ.io.deq.bits.bits, enqBitsLast)
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reference.io.deq.ready := targetFire && deqRevQ.io.deq.bits
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@ -259,7 +259,7 @@ class ReadyValidChannelUnitTest(
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// that will more closely the FPGA
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val enqCount = RegInit(0.U(log2Ceil(queueDepth + 1).W))
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val memFullyDefined = enqCount === queueDepth.U
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enqCount := Mux(!memFullyDefined && reference.io.enq.fire && !reference.reset.toBool, enqCount + 1.U, enqCount)
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enqCount := Mux(!memFullyDefined && reference.io.enq.fire && !reference.reset.asBool, enqCount + 1.U, enqCount)
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// Track the target cycle at which all entries are known
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val memFullyDefinedCycle = RegInit(1.U(log2Ceil(2*timeout).W))
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@ -7,8 +7,6 @@ import junctions._
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import midas.widgets._
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import chisel3._
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import chisel3.util._
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import chisel3.core.ActualDirection
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import chisel3.core.DataMirror.directionOf
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.diplomacy._
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@ -299,7 +299,7 @@ class SimWrapper(val config: SimWrapperConfig)(implicit val p: Parameters) exten
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TargetBoxAnnotation(target.toAbsoluteTarget)
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})
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target.io.hostReset := reset.toBool
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target.io.hostReset := reset.asBool
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target.io.hostClock := clock
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import chisel3.ExplicitCompileOptions.NotStrict // FIXME
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@ -358,9 +358,9 @@ class FASEDMemoryTimingModel(completeConfig: CompleteConfig, hostParams: Paramet
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writeEgress.io.resp.tReady := model.io.egressResp.bReady
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model.io.egressResp.bBits := writeEgress.io.resp.tBits
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ingress.reset := reset.toBool || tReset && tFireHelper.fire(ingressReady)
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readEgress.reset := reset.toBool || tReset && targetFire
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writeEgress.reset := reset.toBool || tReset && targetFire
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ingress.reset := reset.asBool || tReset && tFireHelper.fire(ingressReady)
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readEgress.reset := reset.asBool || tReset && targetFire
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writeEgress.reset := reset.asBool || tReset && targetFire
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if (cfg.params.localHCycleCount) {
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@ -8,6 +8,7 @@ import freechips.rocketchip.unittest.UnitTest
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import junctions._
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import chisel3._
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import chisel3.stage.ChiselGeneratorAnnotation
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import chisel3.util._
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// From MIDAS
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@ -587,7 +588,7 @@ object AddressRangeCounter {
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object AddressCollisionCheckMain extends App {
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implicit val p = Parameters.empty.alterPartial({case NastiKey => NastiParameters(64,32,4)})
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chisel3.Driver.execute(args, () => new AddressCollisionChecker(4,4,16))
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(new chisel3.stage.ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => new AddressCollisionChecker(4,4,16))))
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}
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class CounterTableUnitTest extends UnitTest {
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@ -28,7 +28,7 @@ class AsyncMemChiselRTL(val depth: Int, val dataWidth: Int, val nReads: Int = 2,
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case (detected, cmd) => detected || collides(cmd)
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}
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when (write_cmd.active && !reset.toBool() && !collision_detected) {
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when (write_cmd.active && !reset.asBool() && !collision_detected) {
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data.write(write_cmd.addr, write_cmd.data)
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}
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}
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@ -68,7 +68,7 @@ class AsyncMemChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int =
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val active_write_en = Wire(Bool())
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val read_data_async = data.read(active_read_addr)
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val read_data = RegNext(read_data_async)
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when (active_write_en && !target_reset_value && !reset.toBool()) {
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when (active_write_en && !target_reset_value && !reset.asBool()) {
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data.write(active_write_addr, active_write_data)
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}
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@ -110,7 +110,7 @@ class AsyncMemChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int =
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// Target reset state management
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channels.reset.ready := !target_reset_fired
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when (advance_cycle || reset.toBool()) {
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when (advance_cycle || reset.asBool()) {
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target_reset_fired := false.B
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} .elsewhen (channels.reset.fire) {
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target_reset_fired := true.B
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@ -126,7 +126,7 @@ class AsyncMemChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int =
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channels.read_resps(i).bits := Mux(read_state(i) === active, read_data, read_resp_data(i))
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channels.read_resps(i).valid := read_state(i) === active || read_state(i) === generated
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when (advance_cycle || reset.toBool()) {
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when (advance_cycle || reset.asBool()) {
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read_state(i) := start
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} .elsewhen (read_state(i) === start && read_access_granted(i)) {
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read_state(i) := active
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@ -144,7 +144,7 @@ class AsyncMemChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int =
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active_write_en := false.B
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for (i <- 0 until nWrites) {
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channels.write_cmds(i).ready := write_prereqs_met(i) && !write_complete(i)
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when (advance_cycle || reset.toBool()) {
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when (advance_cycle || reset.asBool()) {
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write_complete(i) := false.B
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} .elsewhen (channels.write_cmds(i).fire) {
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write_complete(i) := true.B
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@ -38,7 +38,7 @@ class RegfileChiselRTL(val depth: Int, val dataWidth: Int, val nReads: Int, val
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val data = Reg(Vec(depth, UInt(dataWidth.W)))
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data.foreach({
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d => when (reset.toBool()) { d := 0.U }
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d => when (reset.asBool()) { d := 0.U }
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})
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(channels.read_cmds zip channels.read_resps).foreach({
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@ -46,7 +46,7 @@ class RegfileChiselRTL(val depth: Int, val dataWidth: Int, val nReads: Int, val
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})
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channels.write_cmds.foreach({
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c => when (c.active && !reset.toBool()) { data(c.addr) := c.data }
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c => when (c.active && !reset.asBool()) { data(c.addr) := c.data }
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})
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}
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@ -135,7 +135,7 @@ class RegfileChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int, va
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// reset, as it is next-ed during host reset. Regardless, early
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// reset is necessary to guard the first read.
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// Also, only reset after reads are done
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when (reset.toBool() || (has_reset_token && read_resps_done_next_cycle && reset_token)) {
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when (reset.asBool() || (has_reset_token && read_resps_done_next_cycle && reset_token)) {
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d := 0.U
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}
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}
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@ -146,7 +146,7 @@ class RegfileChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int, va
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// State updates
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val done = read_resps_done_next_cycle && writes_done_next_cycle && has_reset_token
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def updateState(fired: Bool, fire: Bool): Unit = {
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fired := Mux(reset.toBool() || done, false.B, fired || fire)
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fired := Mux(reset.asBool() || done, false.B, fired || fire)
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}
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(reads_cmd_fired zip reads_cmd_fire).foreach { case (fired, fire) => updateState(fired, fire) }
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@ -6,7 +6,6 @@ package passes
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import midas.core._
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import freechips.rocketchip.config.Parameters
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import chisel3.core.DataMirror.directionOf
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import firrtl._
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import firrtl.annotations._
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@ -10,7 +10,7 @@ import scala.collection.mutable
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import firrtl._
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import firrtl.annotations.{CircuitName, ReferenceTarget, ModuleTarget, InstanceTarget}
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import firrtl.options.Dependency
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import firrtl.stage.Forms
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import firrtl.stage.{FirrtlCircuitAnnotation, Forms}
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import firrtl.stage.transforms.Compiler
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import firrtl.ir._
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import firrtl.Mappers._
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@ -18,6 +18,7 @@ import firrtl.passes.LowerTypes.loweredName
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import firrtl.Utils.{BoolType, splitRef, mergeRef, create_exps, flow, module_type}
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import firrtl.passes.wiring._
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import Utils._
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import chisel3.stage.{ChiselGeneratorAnnotation, NoRunFirrtlCompilerAnnotation}
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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@ -93,9 +94,13 @@ private[passes] class SimulationMapping(targetName: String) extends firrtl.Trans
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// Generate the encapsulating simulator RTL
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lazy val shim = PlatformShim(innerState.annotations, portTypeMap)
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val c3circuit = chisel3.Driver.elaborate(() => LazyModule(shim).module)
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val chirrtl = Parser.parse(chisel3.Driver.emit(c3circuit))
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val annos = PreLinkRenamingAnnotation(Namespace(innerCircuit)) +: c3circuit.annotations.map(_.toFirrtl)
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val annos = (new chisel3.stage.ChiselStage).transform(
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Seq(
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ChiselGeneratorAnnotation(() => LazyModule(shim).module),
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NoRunFirrtlCompilerAnnotation
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)
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) :+ PreLinkRenamingAnnotation(Namespace(innerCircuit))
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val chirrtl = annos.collectFirst { case a: FirrtlCircuitAnnotation => a }.get.circuit
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val transforms = Seq(
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Dependency[Fame1Instances],
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@ -7,8 +7,8 @@ import firrtl.ir._
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import Mappers._
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import Utils._
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import annotations._
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import midas.passes.{PreLinkRenamingAnnotation, PreLinkRenaming}
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import chisel3.stage.{ChiselGeneratorAnnotation, NoRunFirrtlCompilerAnnotation}
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import midas.passes.{PreLinkRenaming, PreLinkRenamingAnnotation}
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import collection.mutable
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@ -191,9 +191,7 @@ class RAMModelInst(name: String, val readPorts: Seq[ReadPort], val writePorts: S
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}
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def elaborateModel(parentCircuitNS: Namespace): Module = {
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val c3circuit = chisel3.Driver.elaborate(() =>
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new midas.models.sram.AsyncMemChiselModel(depth.toInt, dataWidth, readPorts.size, writePorts.size))
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val chirrtl = Parser.parse(chisel3.Driver.emit(c3circuit))
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val chirrtl = chisel3.stage.ChiselStage.convert(new midas.models.sram.AsyncMemChiselModel(depth.toInt, dataWidth, readPorts.size, writePorts.size))
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val state = new MiddleFirrtlCompiler().compile(CircuitState(chirrtl, ChirrtlForm, Nil), Nil)
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require(state.circuit.modules.length == 1)
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state.circuit.modules.collectFirst({
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@ -34,7 +34,7 @@ class RuntimeConfigGenerationPhase extends Phase with ConfigLookup {
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// FASED BridgeAnnotation, and use that to elaborate a memory model
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fasedBridges.headOption.map({ lm =>
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lazy val fasedBridge = lm.module
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chisel3.Driver.elaborate(() => fasedBridge)
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chisel3.stage.ChiselStage.elaborate(fasedBridge)
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fasedBridge.getSettings(runtimeConfigName)
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})
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annotations
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|
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@ -8,8 +8,7 @@ import junctions._
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import chisel3._
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import chisel3.util._
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import chisel3.core.ActualDirection
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import chisel3.core.DataMirror.directionOf
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import chisel3.experimental.DataMirror
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import freechips.rocketchip.config.Parameters
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import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
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@ -21,7 +20,7 @@ object FlattenData {
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def apply[T <: Data](gen: T): Seq[(Data, ActualDirection)] = {
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gen match {
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case a : Aggregate => a.getElements flatMap(e => this(e))
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case e : Element => Seq((e, directionOf(e)))
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case e : Element => Seq((e, DataMirror.directionOf(e)))
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case _ => throw new RuntimeException("Cannot handle this type")
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}
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}
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@ -37,10 +36,10 @@ object ScanRegister {
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def apply(data: Seq[Data], scanEnable: Bool, scanIn: Bool): Bool = {
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val leaves = data flatMap FlattenData.apply
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leaves.foldLeft(scanIn)((in: Bool, leaf: (Data, ActualDirection)) => {
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val r = Reg(VecInit(leaf._1.asUInt.toBools).cloneType)
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val r = Reg(VecInit(leaf._1.asUInt.asBools).cloneType)
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(leaf._2) match {
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case ActualDirection.Output =>
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r := VecInit(leaf._1.asUInt.toBools)
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r := VecInit(leaf._1.asUInt.asBools)
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case ActualDirection.Input =>
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leaf._1 := r.asUInt
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case _ => throw new RuntimeException("Directions on all elements must be specified")
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|
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@ -5,8 +5,7 @@ package widgets
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import chisel3._
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import chisel3.util._
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||||
import chisel3.core.ActualDirection
|
||||
import chisel3.core.DataMirror.directionOf
|
||||
import chisel3.experimental.DataMirror
|
||||
import junctions._
|
||||
import freechips.rocketchip.config.{Parameters, Field}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
@ -77,7 +76,7 @@ abstract class WidgetImp(wrapper: Widget) extends LazyModuleImp(wrapper) {
|
|||
// For outputs, direct binds the wire to the map
|
||||
def attachIO(io: Record, prefix: String = ""): Unit = {
|
||||
def innerAttachIO(node: Data, name: String): Unit = node match {
|
||||
case (b: Bits) => (directionOf(b): @unchecked) match {
|
||||
case (b: Bits) => (DataMirror.directionOf(b): @unchecked) match {
|
||||
case ActualDirection.Output => attach(b, s"${name}", ReadOnly)
|
||||
case ActualDirection.Input => genWOReg(b, name)
|
||||
}
|
||||
|
|
|
@ -5,6 +5,8 @@ package midas.rocketchip.util
|
|||
import Chisel._
|
||||
import chisel3.RawModule
|
||||
import chisel3.internal.firrtl.Circuit
|
||||
import chisel3.stage.ChiselCircuitAnnotation
|
||||
import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
|
||||
// TODO: better job of Makefrag generation for non-RocketChip testing platforms
|
||||
import java.io.{File, FileWriter}
|
||||
|
||||
|
@ -58,7 +60,7 @@ trait HasGeneratorUtilities {
|
|||
case l: LazyModule => LazyModule(l).module
|
||||
}
|
||||
|
||||
Driver.elaborate(top)
|
||||
chisel3.stage.ChiselStage.elaborate(top())
|
||||
}
|
||||
|
||||
def enumerateROMs(circuit: Circuit): String = {
|
||||
|
@ -110,7 +112,14 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
|
|||
|
||||
/** Output FIRRTL, which an external compiler can turn into Verilog. */
|
||||
def generateFirrtl {
|
||||
Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
|
||||
val w = new FileWriter(new File(s"$longName.fir"))
|
||||
w.write((new chisel3.stage.ChiselStage).execute(Array("-X", "high") ++ args, Seq(ChiselCircuitAnnotation(circuit)))
|
||||
.collect {
|
||||
case EmittedFirrtlCircuitAnnotation(a) => a
|
||||
case EmittedFirrtlModuleAnnotation(a) => a
|
||||
}.map(_.value)
|
||||
.mkString(""))
|
||||
w.close()
|
||||
}
|
||||
|
||||
def generateAnno {
|
||||
|
|
|
@ -292,8 +292,8 @@ object TriggerSource {
|
|||
* debits issued while the module's implicit reset is asserted are not
|
||||
* counted.
|
||||
*/
|
||||
def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.toBool))
|
||||
def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.toBool))
|
||||
def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool))
|
||||
def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool))
|
||||
def apply(creditSig: Bool, debitSig: Bool): Unit = {
|
||||
credit(creditSig)
|
||||
debit(debitSig)
|
||||
|
|
|
@ -73,7 +73,7 @@ class AXI4FuzzerDUT(implicit p: Parameters) extends LazyModule with HasFuzzTarge
|
|||
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
|
||||
axi4.ar.bits.addr.getWidth,
|
||||
axi4.ar.bits.id.getWidth)
|
||||
val fasedInstance = FASEDBridge(clock, axi4, reset.toBool,
|
||||
val fasedInstance = FASEDBridge(clock, axi4, reset.asBool,
|
||||
CompleteConfig(p(firesim.configs.MemModelKey),
|
||||
nastiKey,
|
||||
Some(AXI4EdgeSummary(edge)),
|
||||
|
|
|
@ -4,7 +4,6 @@ package firesim.midasexamples
|
|||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import chisel3.core.MultiIOModule
|
||||
|
||||
import midas.targetutils.{PerfCounter, AutoCounterCoverModuleAnnotation}
|
||||
import freechips.rocketchip.util.property._
|
||||
|
@ -70,7 +69,7 @@ class AutoCounterModuleDUT(
|
|||
}
|
||||
}
|
||||
|
||||
class AutoCounterModuleChild extends MultiIOModule {
|
||||
class AutoCounterModuleChild extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val c = Input(Bool())
|
||||
val oddlfsr = Output(Bool())
|
||||
|
|
|
@ -4,8 +4,7 @@ package firesim.midasexamples
|
|||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import chisel3.util.unless
|
||||
import chisel3.experimental.{withClock, annotate}
|
||||
import chisel3.experimental.annotate
|
||||
|
||||
import midas.widgets.PeekPokeBridge
|
||||
import midas.targetutils.FAMEModelAnnotation
|
||||
|
@ -23,7 +22,7 @@ class GCDInner extends Module {
|
|||
val x = Reg(UInt())
|
||||
val y = Reg(UInt())
|
||||
when (x > y) { x := x - y }
|
||||
unless (x > y) { y := y - x }
|
||||
when (x <= y) { y := y - x }
|
||||
when (io.e) { x := io.a; y := io.b }
|
||||
io.z := x
|
||||
io.v := y === 0.U
|
||||
|
|
|
@ -16,7 +16,7 @@ class MulticlockAutoCounterModule(implicit p: Parameters) extends RawModule {
|
|||
val clockBridge = RationalClockBridge(RationalClock("ThirdRate", 1, 3))
|
||||
val List(refClock, div2Clock) = clockBridge.io.clocks.toList
|
||||
val reset = WireInit(false.B)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.toBool)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.asBool)
|
||||
// Used to let printfs that emit the correct validation output
|
||||
val instPath = "MulticlockAutoCounterModule_AutoCounterModuleDUT"
|
||||
withClockAndReset(refClock, reset) {
|
||||
|
|
|
@ -16,7 +16,7 @@ class MulticlockPrintfModule(implicit p: Parameters) extends RawModule {
|
|||
val clockBridge = RationalClockBridge(RationalClock("HalfRate",1 , 2))
|
||||
val List(refClock, div2Clock) = clockBridge.io.clocks.toList
|
||||
val reset = WireInit(false.B)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.toBool)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.asBool)
|
||||
withClockAndReset(refClock, reset) {
|
||||
val lfsr = chisel3.util.random.LFSR(16)
|
||||
val fullRateMod = Module(new PrintfModuleDUT)
|
||||
|
|
|
@ -4,7 +4,6 @@ package firesim.midasexamples
|
|||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import chisel3.experimental.{withClock}
|
||||
import junctions._
|
||||
import freechips.rocketchip.config.{Parameters, Field}
|
||||
|
||||
|
|
|
@ -42,8 +42,8 @@ class TriggerSourceModule extends MultiIOModule {
|
|||
// Note one could alternatively write: TriggerSource(start, stop)
|
||||
// DOC include end: TriggerSource Usage
|
||||
|
||||
referenceCredit := ~reset.toBool && start
|
||||
referenceDebit := ~reset.toBool && stop
|
||||
referenceCredit := ~reset.asBool && start
|
||||
referenceDebit := ~reset.asBool && stop
|
||||
}
|
||||
|
||||
class LevelSensitiveTriggerSourceModule extends MultiIOModule {
|
||||
|
@ -104,7 +104,7 @@ class TriggerWiringModule(implicit p: Parameters) extends RawModule {
|
|||
val refSourceCounts = new mutable.ArrayBuffer[ReferenceSourceCounters]()
|
||||
val refSinks = new mutable.ArrayBuffer[Bool]()
|
||||
val reset = WireInit(false.B)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.toBool)
|
||||
val resetHalfRate = ResetCatchAndSync(div2Clock, reset.asBool)
|
||||
withClockAndReset(refClock, reset) {
|
||||
val peekPokeBridge = PeekPokeBridge(refClock, reset)
|
||||
val src = Module(new TriggerSourceModule)
|
||||
|
|
|
@ -4,8 +4,7 @@ package firesim.midasexamples
|
|||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import chisel3.util.unless
|
||||
import chisel3.experimental.{withClock, annotate}
|
||||
import chisel3.experimental.annotate
|
||||
|
||||
import midas.widgets.PeekPokeBridge
|
||||
import midas.targetutils._
|
||||
|
|
|
@ -3,7 +3,6 @@
|
|||
package firesim.midasexamples
|
||||
|
||||
import chisel3._
|
||||
import chisel3.experimental.{withClock}
|
||||
|
||||
import midas.widgets.{RationalClockBridge, PeekPokeBridge}
|
||||
|
||||
|
@ -16,6 +15,8 @@ class PeekPokeMidasExampleHarness(dutGen: () => Module) extends RawModule {
|
|||
|
||||
withClockAndReset(clock, reset) {
|
||||
val dut = Module(dutGen())
|
||||
val peekPokeBridge = PeekPokeBridge(clock, reset, ("io", dut.io))
|
||||
val peekPokeBridge = PeekPokeBridge(clock, reset, chisel3.experimental.DataMirror.modulePorts(dut).filterNot {
|
||||
case (name, _) => name == "clock" | name == "reset"
|
||||
}:_*)
|
||||
}
|
||||
}
|
||||
|
|
|
@ -4,8 +4,7 @@ package firesim.midasexamples
|
|||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import chisel3.util.{unless, HasBlackBoxInline}
|
||||
import chisel3.experimental.{withClockAndReset}
|
||||
import chisel3.util.HasBlackBoxInline
|
||||
|
||||
import midas.widgets.PeekPokeBridge
|
||||
|
||||
|
|
Loading…
Reference in New Issue