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Debugging Using FPGA Integrate Logic Analyzers (ILA)
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=======================================
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Sometimes it takes too long to simulate FireSim on RTL simulators, and
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in some occasions we would also like to debug the simulation infrastructure
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itself. For these purposes, we can use the Xilinx Integrated Logic Analyzer
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resources on the FPGA.
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ILAs allows real time sampling of pre-selected signals during FPGA runtime,
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and provided and interface for setting trigger and viewing samples waveforms
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from the FPGA. For more information about ILAs, please refer to the Xilinx
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guide on the topic
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Midas provides custom Chisel annotations which allow annotating signals in the
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Chisel source code, which will automatically generate custom ILA IP for the
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fpga, and then transforme and wire the relevant signals to the ILA.
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ILAs consume FPGA resources, and therefore it is recommended not to annotate a
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large number of signals.
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Annotating Signals
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------------------------
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In order to annotate a signal, we must import ``midas.passes.FpgaDebugAnnotation``.
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We then simply add a relevant ``FpgaDebugAnnotation(<selected_signal>)`` with the
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desired signal as an argument.
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Example:
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::
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import midas.passes.FpgaDebugAnnotation
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class SomeModuleIO(implicit p: Parameters) extends SomeIO()(p){
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val out1 = Output(Bool())
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val in1 = Input(Bool())
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chisel3.experimental.annotate(FpgaDebugAnnotation(out1))
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}
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Note: In case the module with the annotated signal is instantiated multiple times,
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all instatiations of the annotated signal will be wired to the ILA.
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Using the ILA at Runtime
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------------------------
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In order to use the ILA, we must enable the GUI interface on our manager instance.
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This can be done by running the command:
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::
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/home/centos/src/scripts/setup_gui.sh
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When the command will finish running, a temporary password will be printed out. This
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password will be used to access the GUI interface of the master instance. We will
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connect to the GUI interface of the manager instance using an RDP client. Use the
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public IP address of the manager instances in order to connect using the RDP client.
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The username is `centos`, and the password is the temporary password that was printed
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out at the end of the previous command. An additional login screen with the username
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Cloud-User and the same password may appear in some occasion. More information about
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the AWS GUI interface can be found in the ``~/src/GUI_README`` on the manager instance.
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After access the GUI interface, open a terminal, and open ``vivado``.
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Follow the instructions in the `AWS-FPGA guide for connecting xilinx hardware manager on vivado (running on a remote machine) to the debug target <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md#connecting-xilinx-hardware-manager-vivado-lab-edition-running-on-a-remote-machine-to-the-debug-target-fpga-enabled-ec2-instance>`__ .
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where ``<hostname or IP address>`` is the internal IP of the simulation instance (not
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the manager instance. i.e. The IP starting with 192.168.X.X).
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The probes file can be found in the manager instance under the path
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``firesim/deploy/results-build/<build_identifier>/cl_firesim/build/checkpoints/<probes_file.ltx>``
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Select the ILA with the description of `WRAPPER_INST/CL/CL_FIRESIM_DEBUG_WIRING_TRANSFORM`, and you may now use the ILA just as if it was on
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a local FPGA.
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@ -115,7 +115,6 @@ Run rv64ui-p-simple (a single assembly test) on a VCS simulator with waveform du
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::
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make DESIGN=FireSimNoNIC vcs-debug
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make EMUL=vcs $(pwd)/output/f1/FireSimNoNIC-FireSimRocketChipConfig-FireSimConfig/rv64ui-p-simple.vpd
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@ -221,3 +220,79 @@ To run only the MIDAS examples:
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testOnly firesim.midasexamples.*
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Debugging Using FPGA Integrated Logic Analyzers (ILA)
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=======================================
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Sometimes it takes too long to simulate FireSim on RTL simulators, and
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in some occasions we would also like to debug the simulation infrastructure
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itself. For these purposes, we can use the Xilinx Integrated Logic Analyzer
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resources on the FPGA.
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ILAs allows real time sampling of pre-selected signals during FPGA runtime,
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and provided and interface for setting trigger and viewing samples waveforms
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from the FPGA. For more information about ILAs, please refer to the Xilinx
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guide on the topic
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Midas provides custom Chisel annotations which allow annotating signals in the
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Chisel source code, which will automatically generate custom ILA IP for the
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fpga, and then transforme and wire the relevant signals to the ILA.
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ILAs consume FPGA resources, and therefore it is recommended not to annotate a
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large number of signals.
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Annotating Signals
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------------------------
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In order to annotate a signal, we must import ``midas.passes.FpgaDebugAnnotation``.
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We then simply add a relevant ``FpgaDebugAnnotation(<selected_signal>)`` with the
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desired signal as an argument.
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Example:
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::
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import midas.passes.FpgaDebugAnnotation
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class SomeModuleIO(implicit p: Parameters) extends SomeIO()(p){
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val out1 = Output(Bool())
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val in1 = Input(Bool())
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chisel3.experimental.annotate(FpgaDebugAnnotation(out1))
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}
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Note: In case the module with the annotated signal is instantiated multiple times,
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all instatiations of the annotated signal will be wired to the ILA.
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Using the ILA at Runtime
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------------------------
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In order to use the ILA, we must enable the GUI interface on our manager instance.
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This can be done by running the command:
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::
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/home/centos/src/scripts/setup_gui.sh
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When the command will finish running, a temporary password will be printed out. This
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password will be used to access the GUI interface of the master instance. We will
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connect to the GUI interface of the manager instance using an RDP client. Use the
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public IP address of the manager instances in order to connect using the RDP client.
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The username is `centos`, and the password is the temporary password that was printed
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out at the end of the previous command. An additional login screen with the username
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Cloud-User and the same password may appear in some occasion. More information about
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the AWS GUI interface can be found in the ``~/src/GUI_README`` on the manager instance.
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After access the GUI interface, open a terminal, and open ``vivado``.
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Follow the instructions in the `AWS-FPGA guide for connecting xilinx hardware manager on vivado (running on a remote machine) to the debug target <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md#connecting-xilinx-hardware-manager-vivado-lab-edition-running-on-a-remote-machine-to-the-debug-target-fpga-enabled-ec2-instance>`__ .
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where ``<hostname or IP address>`` is the internal IP of the simulation instance (not
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the manager instance. i.e. The IP starting with 192.168.X.X).
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The probes file can be found in the manager instance under the path
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``firesim/deploy/results-build/<build_identifier>/cl_firesim/build/checkpoints/<probes_file.ltx>``
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Select the ILA with the description of `WRAPPER_INST/CL/CL_FIRESIM_DEBUG_WIRING_TRANSFORM`, and you may now use the ILA just as if it was on
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a local FPGA.
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@ -25,7 +25,7 @@ New to FireSim? Jump to the :ref:`firesim-basics` page for more info.
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Advanced-Usage/Manager/index
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Advanced-Usage/Workloads/index
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Advanced-Usage/Generating-Different-Targets.rst
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Advanced-Usage/RTL-Simulation
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Advanced-Usage/Debugging.rst
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Developing-New-Devices/index
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Advanced-Usage/Supernode.rst
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Advanced-Usage/Miscellaneous-Tips.rst
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