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Merge pull request #446 from firesim/triggers-counters-integration-clean 

Bring back file check for more robust TracerV disable
This commit is contained in:
alonamid 2019-12-22 11:06:05 -08:00 committed by GitHub
parent 0063a40fd0 3764407bbf
commit b4ca7e630c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 16 additions and 6 deletions
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18
sim/firesim-lib/src/main/cc/bridges/tracerv.cc
View File

@ -159,7 +159,11 @@ void tracerv_t::tick() {
if (outfull) {
// TODO. as opt can mmap file and just load directly into it.
pull(dma_addr, (char*)OUTBUF, QUEUE_DEPTH * 64);
if (this->human_readable || this->test_output) {
//check that a tracefile exists (one is enough) since the manager
//does not create a tracefile when trace_enable is disabled, but the
//TracerV bridge still exists, and no tracefiles are create be default.
if (this->tracefiles[0]) {
if (this->human_readable || this->test_output) {
for (int i = 0; i < QUEUE_DEPTH * 8; i+=8) {
if (this->test_output) {
fprintf(this->tracefiles[0], "TRACEPORT: ");
@ -179,7 +183,7 @@ void tracerv_t::tick() {
}
}
}
} else {
} else {
for (int i = 0; i < QUEUE_DEPTH * 8; i+=8) {
// this stores as raw binary. stored as little endian.
// e.g. to get the same thing as the human readable above,
@ -188,6 +192,7 @@ void tracerv_t::tick() {
fwrite(OUTBUF + (i+q), sizeof(uint64_t), 1, this->tracefiles[0]);
}
}
}
}
cur_cycle += QUEUE_DEPTH;
}
@ -214,7 +219,11 @@ void tracerv_t::flush() {
// TODO. as opt can mmap file and just load directly into it.
pull(dma_addr, (char*)OUTBUF, beats_available * 64);
if (this->human_readable || this->test_output) {
//check that a tracefile exists (one is enough) since the manager
//does not create a tracefile when trace_enable is disabled, but the
//TracerV bridge still exists, and no tracefiles are create be default.
if (this->tracefiles[0]) {
if (this->human_readable || this->test_output) {
for (int i = 0; i < beats_available * 8; i+=8) {
if (this->test_output) {
@ -235,7 +244,7 @@ void tracerv_t::flush() {
}
}
}
} else {
} else {
for (int i = 0; i < QUEUE_DEPTH * 8; i+=8) {
// this stores as raw binary. stored as little endian.
// e.g. to get the same thing as the human readable above,
@ -244,6 +253,7 @@ void tracerv_t::flush() {
fwrite(OUTBUF + (i+q), sizeof(uint64_t), 1, this->tracefiles[q]);
}
}
}
}
cur_cycle += beats_available;
}

4
sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala
View File

@ -197,9 +197,9 @@ class TracerVBridgeModule(key: TracerVKey)(implicit p: Parameters) extends Bridg
val triggerInstValVec = RegInit(VecInit(Seq.fill(traces.length)(false.B)))
traces.zipWithIndex.foreach { case (trace, i) =>
when (trace.valid) {
when (hostTriggerStartInst === (trace.insn & hostTriggerStartInstMask)) {
when !((hostTriggerStartInst ^ trace.insn) & hostTriggerStartInstMask).orR {
triggerInstValVec(i) := true.B
} .elsewhen (hostTriggerEndInst === (trace.insn & hostTriggerEndInstMask)) {
} .elsewhen !((hostTriggerEndInst ^ trace.insn) & hostTriggerEndInstMask).orR {
triggerInstValVec(i) := false.B
}
}