cleanup
This commit is contained in:
Sagar Karandikar
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@ -83,15 +83,27 @@ Choose your platform to get started
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FireSim supports many types of FPGAs and FPGA platforms! Click one of the following links to work through the getting started guide for your particular platform.
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* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index`. Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index`
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* Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`
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* Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs`. Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs`
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* Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs`. Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs`
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* Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs`. Status: ✅ All FireSim Features Supported.
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* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs`
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* Status: ✅ All FireSim Features Supported.
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* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs`. Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`.
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* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs`
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* Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`.
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@ -1,8 +1,8 @@
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|fpga_name| Getting Started Guide
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============================================================================================
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The getting started guides that follow this page will walk you through the complete flow for
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getting an example FireSim simulation up and running using an on-premises |fpga_name|_ FPGA,
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The getting started guides that follow this page will walk you through the complete (|flow_name|) flow for
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getting an example FireSim simulation up and running using an on-premises |fpga_name_short|_ FPGA,
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from scratch.
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First, we'll set up your environment, then run a simulation of a single RISC-V Rocket-based
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@ -1,5 +1,7 @@
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.. |fpga_name| replace:: RHS Research Nitefury II XDMA-based
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.. _fpga_name: https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m
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.. |fpga_name_short| replace:: RHS Research Nitefury II
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.. _fpga_name_short: https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m
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.. |flow_name| replace:: XDMA-based
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.. |bit_type| replace:: ``bitstream_tar``
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.. |build_type| replace:: Xilinx Vivado
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@ -1,5 +1,7 @@
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.. |fpga_name| replace:: Xilinx Alveo U250 XDMA-based
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.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html
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.. |fpga_name_short| replace:: Xilinx Alveo U250
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.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html
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.. |flow_name| replace:: XDMA-based
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.. |bit_type| replace:: ``bitstream_tar``
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.. |build_type| replace:: Xilinx Vivado
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@ -1,5 +1,7 @@
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.. |fpga_name| replace:: Xilinx Alveo U280 XDMA-based
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.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html
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.. |fpga_name_short| replace:: Xilinx Alveo U280
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.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html
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.. |flow_name| replace:: XDMA-based
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.. |bit_type| replace:: ``bitstream_tar``
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.. |build_type| replace:: Xilinx Vivado
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@ -1,5 +1,7 @@
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.. |fpga_name| replace:: Xilinx VCU118 XDMA-based
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.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/vcu118.html
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.. |fpga_name_short| replace:: Xilinx VCU118
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.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/vcu118.html
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.. |flow_name| replace:: XDMA-based
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.. |bit_type| replace:: ``bitstream_tar``
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.. |build_type| replace:: Xilinx Vivado
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@ -1,5 +1,7 @@
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.. |fpga_name| replace:: (Experimental) Xilinx Alveo U250 Vitis-based
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.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html
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.. |fpga_name_short| replace:: Xilinx Alveo U250
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.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html
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.. |flow_name| replace:: Vitis-based
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.. |bit_type| replace:: ``xclbin``
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.. |build_type| replace:: Xilinx Vitis
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@ -21,7 +23,7 @@
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#. **Single-node simulation guide**: This guide walks you through the
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process of running one simulation locally consisting of a single
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|fpga_name|, using our pre-built public FireSim |bit_type| bitstream.
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|fpga_name_short|, using our pre-built public FireSim |bit_type| bitstream.
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#. **Building your own hardware designs guide (Chisel to FPGA Image)**:
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This guide walks you through the full process of taking Rocket Chip RTL
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