diff --git a/docs/FireSim-Basics.rst b/docs/FireSim-Basics.rst index b0db63aa..582b1653 100644 --- a/docs/FireSim-Basics.rst +++ b/docs/FireSim-Basics.rst @@ -83,15 +83,27 @@ Choose your platform to get started FireSim supports many types of FPGAs and FPGA platforms! Click one of the following links to work through the getting started guide for your particular platform. -* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index`. Status: ✅ All FireSim Features Supported. +* :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index` + + * Status: ✅ All FireSim Features Supported. -* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. Status: ✅ All FireSim Features Supported. +* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs` + + * Status: ✅ All FireSim Features Supported. -* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs`. Status: ✅ All FireSim Features Supported. +* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs` + + * Status: ✅ All FireSim Features Supported. -* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs`. Status: ✅ All FireSim Features Supported. +* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs` + + * Status: ✅ All FireSim Features Supported. -* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs`. Status: ✅ All FireSim Features Supported. +* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs` + + * Status: ✅ All FireSim Features Supported. -* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs`. Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. +* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs` + + * Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Intro-Template.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Intro-Template.rst index fe43f652..2737f34c 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Intro-Template.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Intro-Template.rst @@ -1,8 +1,8 @@ |fpga_name| Getting Started Guide ============================================================================================ -The getting started guides that follow this page will walk you through the complete flow for -getting an example FireSim simulation up and running using an on-premises |fpga_name|_ FPGA, +The getting started guides that follow this page will walk you through the complete (|flow_name|) flow for +getting an example FireSim simulation up and running using an on-premises |fpga_name_short|_ FPGA, from scratch. First, we'll set up your environment, then run a simulation of a single RISC-V Rocket-based diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.rst index d76ca3d4..810c7e2c 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.rst @@ -1,5 +1,7 @@ .. |fpga_name| replace:: RHS Research Nitefury II XDMA-based -.. _fpga_name: https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m +.. |fpga_name_short| replace:: RHS Research Nitefury II +.. _fpga_name_short: https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m +.. |flow_name| replace:: XDMA-based .. |bit_type| replace:: ``bitstream_tar`` .. |build_type| replace:: Xilinx Vivado diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs.rst index c3198443..e4f64134 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs.rst @@ -1,5 +1,7 @@ .. |fpga_name| replace:: Xilinx Alveo U250 XDMA-based -.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html +.. |fpga_name_short| replace:: Xilinx Alveo U250 +.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html +.. |flow_name| replace:: XDMA-based .. |bit_type| replace:: ``bitstream_tar`` .. |build_type| replace:: Xilinx Vivado diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs.rst index 6d93e5a9..46b1835b 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs.rst @@ -1,5 +1,7 @@ .. |fpga_name| replace:: Xilinx Alveo U280 XDMA-based -.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html +.. |fpga_name_short| replace:: Xilinx Alveo U280 +.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html +.. |flow_name| replace:: XDMA-based .. |bit_type| replace:: ``bitstream_tar`` .. |build_type| replace:: Xilinx Vivado diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs.rst index 81f3a6db..30aa4e6a 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs.rst @@ -1,5 +1,7 @@ .. |fpga_name| replace:: Xilinx VCU118 XDMA-based -.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/vcu118.html +.. |fpga_name_short| replace:: Xilinx VCU118 +.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/vcu118.html +.. |flow_name| replace:: XDMA-based .. |bit_type| replace:: ``bitstream_tar`` .. |build_type| replace:: Xilinx Vivado diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs.rst index 977fd421..7e6c7e03 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs.rst @@ -1,5 +1,7 @@ .. |fpga_name| replace:: (Experimental) Xilinx Alveo U250 Vitis-based -.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html +.. |fpga_name_short| replace:: Xilinx Alveo U250 +.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html +.. |flow_name| replace:: Vitis-based .. |bit_type| replace:: ``xclbin`` .. |build_type| replace:: Xilinx Vitis @@ -21,7 +23,7 @@ #. **Single-node simulation guide**: This guide walks you through the process of running one simulation locally consisting of a single - |fpga_name|, using our pre-built public FireSim |bit_type| bitstream. + |fpga_name_short|, using our pre-built public FireSim |bit_type| bitstream. #. **Building your own hardware designs guide (Chisel to FPGA Image)**: This guide walks you through the full process of taking Rocket Chip RTL