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Merge remote-tracking branch 'origin/dev' into triggers-counters-integration-clean

This commit is contained in:
David Biancolin 2019-12-16 11:23:46 -08:00
parent 40b07d974f 5919522451
commit a400d1ccff
49 changed files with 87 additions and 123 deletions
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2
build-setup-nolog.sh
View File

@ -61,7 +61,7 @@ do
shift
done
# Disable the REBAR submodule initially, and enable if we're not in library mode
# Disable the Chipyard submodule initially, and enable if we're not in library mode
git config submodule.target-design/chipyard.update none
git config submodule.sw/firesim-software.update none
git submodule update --init --recursive #--jobs 8

1
deploy/runtools/user_topology.py
View File

@ -373,7 +373,6 @@ class UserTopologies(object):
"fireboom-singlecore-no-nic-l2-llc4mb-ddr3",
"fireboom-singlecore-no-nic-l2-llc4mb-ddr3-ramopts",
"firesim-quadcore-no-nic-l2-llc4mb-ddr3",
"firesim-singlecore-no-nic-lbp",
]
assert len(hwdb_entries) == self.no_net_num_nodes
self.roots = [FireSimServerNode(hwdb_entries[x]) for x in range(self.no_net_num_nodes)]

24
deploy/sample-backup-configs/sample_config_build.ini
View File

@ -14,7 +14,7 @@ postbuildhook=
# if you add a build here, it will be built when you run buildafi
# Legacy recipe without an L2
firesim-quadcore-nic-llc4mb-ddr3
firesim-singlecore-no-nic-l2-lbp
#firesim-singlecore-no-nic-l2-lbp
#firesim-singlecore-nic-l2-lbp
#firesim-quadcore-no-nic-l2-lbp
#firesim-quadcore-nic-l2-lbp
@ -29,18 +29,18 @@ fireboom-singlecore-nic-l2-llc4mb-ddr3
firesim-supernode-singlecore-nic-lbp
fireboom-singlecore-no-nic-l2-llc4mb-ddr3-ramopts
# for MICRO 2019 tutorial. May be removed in the future.
firesim-singlecore-sha3-nic-l2-llc4mb-ddr3
firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3
firesim-singlecore-sha3-nic-l2-llc4mb-ddr3-print
firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3-print
#firesim-singlecore-sha3-nic-l2-llc4mb-ddr3
#firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3
#firesim-singlecore-sha3-nic-l2-llc4mb-ddr3-print
#firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3-print
#fireboom-dualcore-no-nic-l2-llc4mb-ddr3
#fireboom-dualcore-nic-l2-llc4mb-ddr3
firerocketboom-1rx1b-no-nic-l2-ddr3-llc4mb
#firerocketboom-1rx1b-no-nic-l2-ddr3-llc4mb
[agfistoshare]
# Legacy recipe without an L2
firesim-quadcore-nic-llc4mb-ddr3
firesim-singlecore-no-nic-l2-lbp
#firesim-singlecore-no-nic-l2-lbp
#firesim-singlecore-nic-l2-lbp
#firesim-quadcore-no-nic-l2-lbp
#firesim-quadcore-nic-l2-lbp
@ -55,13 +55,13 @@ fireboom-singlecore-nic-l2-llc4mb-ddr3
firesim-supernode-singlecore-nic-lbp
fireboom-singlecore-no-nic-l2-llc4mb-ddr3-ramopts
# for MICRO 2019 tutorial. May be removed in the future.
firesim-singlecore-sha3-nic-l2-llc4mb-ddr3
firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3
firesim-singlecore-sha3-nic-l2-llc4mb-ddr3-print
firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3-print
#firesim-singlecore-sha3-nic-l2-llc4mb-ddr3
#firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3
#firesim-singlecore-sha3-nic-l2-llc4mb-ddr3-print
#firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3-print
#fireboom-dualcore-no-nic-l2-llc4mb-ddr3
#fireboom-dualcore-nic-l2-llc4mb-ddr3
firerocketboom-1rx1b-no-nic-l2-ddr3-llc4mb
#firerocketboom-1rx1b-no-nic-l2-ddr3-llc4mb
[sharewithaccounts]
somebodysname=123456789012

42
deploy/sample-backup-configs/sample_config_hwdb.ini
View File

@ -10,62 +10,38 @@
# own images.
[fireboom-singlecore-nic-l2-llc4mb-ddr3]
agfi=agfi-034446a72078958bf
agfi=agfi-0c2f6b68ab3e05ce1
deploytripletoverride=None
customruntimeconfig=None
[fireboom-singlecore-no-nic-l2-llc4mb-ddr3]
agfi=agfi-06b58ae1ea302ace3
agfi=agfi-0fd300a5291689371
deploytripletoverride=None
customruntimeconfig=None
#WNS=-0.059
[fireboom-singlecore-no-nic-l2-llc4mb-ddr3-ramopts]
agfi=agfi-0a06502cc7c58b625
deploytripletoverride=None
customruntimeconfig=None
[firerocketboom-1rx1b-no-nic-l2-ddr3-llc4mb]
agfi=agfi-0cc77cc4cf98bd869
agfi=agfi-0ec8da7c31970e3fb
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-nic-l2-llc4mb-ddr3]
agfi=agfi-0df8a925e514efb6a
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-no-nic-l2-llc4mb-ddr3]
agfi=agfi-0a8470ccd41803f9d
agfi=agfi-044eecdc39b79ad35
deploytripletoverride=None
customruntimeconfig=None
[firesim-quadcore-nic-llc4mb-ddr3]
agfi=agfi-0dae3e34749496fe0
agfi=agfi-024a15cc866e655f1
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-sha3-nic-l2-llc4mb-ddr3]
agfi=agfi-0b3b731fbbc3534cf
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-sha3-nic-l2-llc4mb-ddr3-print]
agfi=agfi-02cb8a85c9dc309ec
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3]
agfi=agfi-0b22b8732efd763df
deploytripletoverride=None
customruntimeconfig=None
[firesim-singlecore-sha3-no-nic-l2-llc4mb-ddr3-print]
agfi=agfi-0120c872049eac274
[firesim-quadcore-no-nic-l2-llc4mb-ddr3]
agfi=agfi-07eb8be281077408b
deploytripletoverride=None
customruntimeconfig=None
[firesim-supernode-singlecore-nic-lbp]
agfi=agfi-0ef33fc78be7fe4e7
agfi=agfi-068b10173d568dabd
deploytripletoverride=None
customruntimeconfig=None

4
deploy/workloads/linux-poweroff-all-no-nic.ini
View File

@ -7,7 +7,7 @@ runfarmtag=linuxpoweroffallnonictargets
f1_16xlarges=0
m4_16xlarges=0
f1_4xlarges=0
f1_2xlarges=4
f1_2xlarges=3
runinstancemarket=ondemand
spotinterruptionbehavior=terminate
@ -15,7 +15,7 @@ spotmaxprice=ondemand
[targetconfig]
topology=all_no_net_targets_config
no_net_num_nodes=4
no_net_num_nodes=3
linklatency=6405
switchinglatency=10
netbandwidth=200

10
sim/Makefile
View File

@ -31,17 +31,17 @@ PLATFORM ?= f1
ifdef FIRESIM_STANDALONE
base_dir := $(firesim_base_dir)
chipyard_dir := $(firesim_base_dir)/target-rtl/chipyard
chipyard_dir := $(abspath ..)/target-design/chipyard
rocketchip_dir := $(chipyard_dir)/generators/rocket-chip
JVM_MEMORY ?= 16G
SCALA_VERSION ?= 2.12.4
SCALA_VERSION ?= 2.12.10
JAVA_ARGS ?= -Xmx$(JVM_MEMORY)
SBT ?= java $(JAVA_ARGS) -jar $(rocketchip_dir)/sbt-launch.jar ++$(SCALA_VERSION)
# Manage the FIRRTL dependency manually
FIRRTL_SUBMODULE_DIR ?= $(firesim_base_dir)/target-rtl/chipyard/tools/firrtl
FIRRTL_JAR ?= $(firesim_base_dir)/target-rtl/chipyard/lib/firrtl.jar
FIRRTL_SUBMODULE_DIR ?= $(chipyard_dir)/tools/firrtl
FIRRTL_JAR ?= $(chipyard_dir)/lib/firrtl.jar
$(FIRRTL_JAR): $(shell find $(FIRRTL_SUBMODULE_DIR)/src/main/scala -iname "*.scala")
$(MAKE) -C $(FIRRTL_SUBMODULE_DIR) SBT="$(SBT)" root_dir=$(FIRRTL_SUBMODULE_DIR) build-scala
touch $(FIRRTL_SUBMODULE_DIR)/utils/bin/firrtl.jar
@ -52,7 +52,7 @@ firrtl: $(FIRRTL_JAR)
.PHONY: firrtl
else
# REBAR make variables
# Chipyard make variables
base_dir := $(abspath ../../..)
sim_dir := $(firesim_base_dir)
chipyard_dir := $(base_dir)

6
sim/build.sbt
View File

@ -3,10 +3,10 @@ import Tests._
lazy val commonSettings = Seq(
organization := "berkeley",
version := "1.0",
scalaVersion := "2.12.4",
scalaVersion := "2.12.10",
traceLevel := 15,
scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test",
libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test",
libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.1",
libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
@ -31,7 +31,7 @@ lazy val firesimAsLibrary = sys.env.get("FIRESIM_STANDALONE") == None
lazy val chipyardDir = if(firesimAsLibrary) {
file("../../../")
} else {
file("target-rtl/chipyard")
file("../target-design/chipyard")
}
lazy val chisel = ProjectRef(chipyardDir, "chisel")

4
sim/firesim-lib/src/main/scala/bridges/SimpleNICBridge.scala
View File

@ -83,7 +83,7 @@ class BigTokenToNICTokenAdapter extends Module {
val pcie_in = Flipped(DecoupledIO(UInt(512.W)))
})
val pcieBundled = (new BIGToken).fromBits(io.pcie_in.bits)
val pcieBundled = io.pcie_in.bits.asTypeOf(new BIGToken)
val xactHelper = DecoupledHelper(io.htnt.ready, io.pcie_in.valid)
@ -235,7 +235,7 @@ class SimpleNICBridgeModule(implicit p: Parameters) extends BridgeModule[HostPor
val pauseThreshold = Reg(UInt(32.W))
val pauseTimes = Reg(UInt(32.W))
target.rlimit := (new RateLimiterSettings).fromBits(rlimitSettings)
target.rlimit := rlimitSettings.asTypeOf(new RateLimiterSettings)
target.macAddr := Cat(macAddrRegUpper, macAddrRegLower)
target.pauser.threshold := pauseThreshold(15, 0)
target.pauser.quanta := pauseTimes(15, 0)

4
sim/firesim-lib/src/main/scala/bridges/UARTBridge.scala
View File

@ -56,7 +56,7 @@ class UARTBridgeModule(key: UARTKey)(implicit p: Parameters) extends BridgeModul
hPort.toHost.hReady := fire
hPort.fromHost.hValid := fire
val sTxIdle :: sTxWait :: sTxData :: sTxBreak :: Nil = Enum(UInt(), 4)
val sTxIdle :: sTxWait :: sTxData :: sTxBreak :: Nil = Enum(4)
val txState = RegInit(sTxIdle)
val txData = Reg(UInt(8.W))
// iterate through bits in byte to deserialize
@ -97,7 +97,7 @@ class UARTBridgeModule(key: UARTKey)(implicit p: Parameters) extends BridgeModul
txfifo.io.enq.bits := txData
txfifo.io.enq.valid := txDataWrap
val sRxIdle :: sRxStart :: sRxData :: Nil = Enum(UInt(), 3)
val sRxIdle :: sRxStart :: sRxData :: Nil = Enum(3)
val rxState = RegInit(sRxIdle)
// iterate using div to convert clock rate to baud
val (rxBaudCount, rxBaudWrap) = Counter(fire, div)

4
sim/firesim-lib/src/main/scala/passes/AsyncResetReg.scala
View File

@ -9,8 +9,8 @@ import firrtl.ir._
import firrtl.Mappers._
import firrtl.transforms._
class AsyncResetReg extends chisel3.experimental.MultiIOModule {
import chisel3.core._
class AsyncResetReg extends chisel3.MultiIOModule {
import chisel3._
import chisel3.util._
val en = IO(Input(Bool()))
val d = IO(Input(Bool()))

2
sim/firesim-lib/src/main/scala/util/Configs.scala
View File

@ -3,8 +3,6 @@ package firesim.util
import java.io.{File, FileWriter}
import chisel3.experimental.RawModule
import freechips.rocketchip.config.{Field, Config}
object DesiredHostFrequency extends Field[Int](90) // Host FPGA frequency, in MHz

1
sim/firesim-lib/src/main/scala/util/DefaultFireSimHarness.scala
View File

@ -3,7 +3,6 @@
package firesim.util
import chisel3._
import chisel3.experimental.RawModule
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}

7
sim/firesim-lib/src/main/scala/util/GeneratorUtils.scala
View File

@ -4,8 +4,7 @@ package firesim.util
import java.io.{File, FileWriter}
import chisel3.Module
import chisel3.experimental.RawModule
import chisel3.{Module, RawModule}
import chisel3.internal.firrtl.Port
import freechips.rocketchip.config.{Config, Parameters}
@ -57,10 +56,10 @@ case class GeneratorArgs(
platformConfigs: String) {
def targetNames(): ParsedInputNames =
ParsedInputNames(targetDir, topModuleProject, topModuleClass, targetConfigProject, targetConfigs)
ParsedInputNames(targetDir, topModuleProject, topModuleClass, targetConfigProject, targetConfigs, None)
def platformNames(): ParsedInputNames =
ParsedInputNames(targetDir, "Unused", "Unused", platformConfigProject, platformConfigs)
ParsedInputNames(targetDir, "Unused", "Unused", platformConfigProject, platformConfigs, None)
def tupleName(): String = s"$topModuleClass-$targetConfigs-$platformConfigs"
}

2
sim/firesim-lib/src/test/scala/TestSuiteCommon.scala
View File

@ -13,7 +13,7 @@ abstract class TestSuiteCommon extends org.scalatest.FlatSpec {
val replayBackends = Seq("rtl")
val platformMakeArgs = Seq(s"PLATFORM=$platformName")
// Check if we are running out of REBAR by checking for the existence of a firesim/sim directory
// Check if we are running out of Chipyard by checking for the existence of a firesim/sim directory
val firesimDir = {
val cwd = System.getProperty("user.dir")
val firesimAsLibDir = new File(cwd, "sims/firesim/sim")

1
sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala
View File

@ -2,7 +2,6 @@
package midas.unittest
import chisel3._
import chisel3.experimental.RawModule
import firrtl.{ExecutionOptionsManager, HasFirrtlOptions}
import freechips.rocketchip.config.{Parameters, Config, Field}

2
sim/midas/src/main/scala/midas/core/Channel.scala
View File

@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink.LFSR64 // Better than chisel's
import chisel3._
import chisel3.util._
import chisel3.experimental.{dontTouch, chiselName, MultiIOModule}
import chisel3.experimental.{chiselName}
import strober.core.{TraceQueue, TraceMaxLen}
import midas.core.SimUtils.{ChLeafType}

1
sim/midas/src/main/scala/midas/core/ClockDomainCrossing.scala
View File

@ -6,7 +6,6 @@ import freechips.rocketchip.tilelink.LFSR64 // Better than chisel's
import chisel3._
import chisel3.util._
import chisel3.experimental.MultiIOModule
trait ClockUtils {
// Assume time is measured in ps

4
sim/midas/src/main/scala/midas/core/SimWrapper.scala
View File

@ -14,7 +14,7 @@ import freechips.rocketchip.config.{Parameters, Field}
import chisel3._
import chisel3.util._
import chisel3.experimental.{MultiIOModule, Direction, ChiselAnnotation}
import chisel3.experimental.{Direction, ChiselAnnotation, annotate}
import chisel3.experimental.DataMirror.directionOf
import firrtl.annotations.{SingleTargetAnnotation, ReferenceTarget}
@ -251,7 +251,7 @@ class SimWrapper(config: SimWrapperConfig)(implicit val p: Parameters) extends M
target.io.hostReset := reset.toBool && hostReset
target.io.clock := clock
import chisel3.core.ExplicitCompileOptions.NotStrict // FIXME
import chisel3.ExplicitCompileOptions.NotStrict // FIXME
def getPipeChannelType(chAnno: FAMEChannelConnectionAnnotation): ChLeafType = {
target.io.wireTypeMap(chAnno)

2
sim/midas/src/main/scala/midas/models/dram/BankConflictModel.scala
View File

@ -96,7 +96,7 @@ class BankConflictModel(cfg: BankConflictConfig)(implicit p: Parameters) extends
transactionQueue.io.enqB.bits.xaction := TransactionMetaData(tNasti.ar.bits)
transactionQueue.io.enqB.bits.bankAddr := io.mmReg.bankAddr.getSubAddr(tNasti.ar.bits.addr)
val bankBusyCycles = Seq.fill(cfg.maxBanks)(RegInit(UInt(0, cfg.maxLatencyBits)))
val bankBusyCycles = Seq.fill(cfg.maxBanks)(RegInit(0.U(cfg.maxLatencyBits.W)))
val bankConflictCounts = RegInit(VecInit(Seq.fill(cfg.maxBanks)(0.U(32.W))))
val newReference = Wire(Decoupled(new BankConflictReference(cfg)))

6
sim/midas/src/main/scala/midas/models/dram/EgressUnit.scala
View File

@ -28,8 +28,8 @@ class FreeList(entries: Int) extends Module {
io.nextId.valid := nextId.valid
io.nextId.bits := nextId.bits
// Add an extra entry to represent the empty bit. Maybe not necessary?
val ids = RegInit(Vec.tabulate(entries)(i =>
if (i == 0) false.B else true.B))
val ids = RegInit(VecInit(Seq.tabulate(entries)(i =>
if (i == 0) false.B else true.B)))
val next = ids.indexWhere((x:Bool) => x)
when(io.nextId.fire() || ~nextId.valid) {
@ -110,7 +110,7 @@ class ReorderBuffer(val numVIds: Int, val numPIds: Int) extends Module {
val trans = new AllocationIO(vIdWidth, pIdWidth)
})
val rat = RegInit(Vec.fill(numPIds)(RATEntry(vIdWidth, pIdWidth)))
val rat = RegInit(VecInit(Seq.fill(numPIds)(RATEntry(vIdWidth, pIdWidth))))
val freeList = Module(new FreeList(numPIds))
freeList.io.freeId <> io.free

3
sim/midas/src/main/scala/midas/models/dram/FASEDMemoryTimingModel.scala
View File

@ -11,7 +11,6 @@ import junctions._
import chisel3._
import chisel3.util._
import chisel3.experimental.dontTouch
import midas.core._
import midas.widgets._
@ -570,7 +569,7 @@ object FASEDBridge {
def apply(axi4: AXI4Bundle, reset: Bool, cfg: CompleteConfig)(implicit p: Parameters): FASEDBridge = {
val ep = Module(new FASEDBridge(cfg)(p.alterPartial({ case NastiKey => cfg.axi4Widths })))
ep.io.reset := reset
import chisel3.core.ExplicitCompileOptions.NotStrict
import chisel3.ExplicitCompileOptions.NotStrict
ep.io.axi4 <> axi4
ep
}

3
sim/midas/src/main/scala/midas/models/dram/Util.scala
View File

@ -9,7 +9,6 @@ import junctions._
import chisel3._
import chisel3.util._
import chisel3.experimental.MultiIOModule
// From MIDAS
import midas.widgets.{D2V, V2D, SkidRegister}
@ -147,7 +146,7 @@ class DynamicLatencyPipe[T <: Data] (
val latencies = Reg(Vec(entries, UInt(countBits.W)))
val pendingRegisters = RegInit(VecInit(Seq.fill(entries)(false.B)))
val done = Vec(latencies.zip(pendingRegisters) map { case (lat, pendingReg) =>
val done = VecInit(latencies.zip(pendingRegisters) map { case (lat, pendingReg) =>
val cycleMatch = lat === io.tCycle
when (cycleMatch) { pendingReg := false.B }
cycleMatch || !pendingReg

1
sim/midas/src/main/scala/midas/models/sram/AsyncMemModel.scala
View File

@ -2,7 +2,6 @@ package midas.models.sram
import chisel3._
import chisel3.util.{Mux1H, Decoupled, RegEnable, log2Ceil, Enum}
import chisel3.experimental.{MultiIOModule, dontTouch}
//import chisel3.experimental.ChiselEnum
import chisel3.experimental.{DataMirror, requireIsChiselType}
import collection.immutable.ListMap

1
sim/midas/src/main/scala/midas/models/sram/ModelGenerator.scala
View File

@ -2,7 +2,6 @@ package midas.models.sram
import chisel3._
import chisel3.util.{Mux1H, Decoupled, RegEnable, log2Ceil}
import chisel3.experimental.MultiIOModule
import chisel3.experimental.{DataMirror, requireIsChiselType}
import collection.immutable.ListMap

3
sim/midas/src/main/scala/midas/models/sram/RegfileModel.scala
View File

@ -2,7 +2,6 @@ package midas.models.sram
import chisel3._
import chisel3.util.{Mux1H, Decoupled, RegEnable, log2Ceil}
import chisel3.experimental.MultiIOModule
import chisel3.experimental.{DataMirror, requireIsChiselType}
import collection.immutable.ListMap
@ -73,7 +72,7 @@ class RegfileChiselModel(val depth: Int, val dataWidth: Int, val nReads: Int, va
// Registers to track target reset -> gates clocks and resets registers
val reset_token = Reg(Bool())
val has_reset_token = Reg(init = false.B)
val has_reset_token = RegInit(false.B)
// Unpacking inputs
val reads_cmd_valid = (0 until nReads).map(i => channels.read_cmds(i).valid)

2
sim/midas/src/main/scala/midas/passes/MidasTransforms.scala
View File

@ -90,7 +90,7 @@ private[midas] class MidasTransforms(implicit p: Parameters) extends Transform {
*
* This uses the legacy non-LI-BDN F1 transform
*/
case class Fame1ChiselAnnotation(target: chisel3.experimental.RawModule, tFire: String = "targetFire")
case class Fame1ChiselAnnotation(target: chisel3.RawModule, tFire: String = "targetFire")
extends chisel3.experimental.ChiselAnnotation {
def toFirrtl = Fame1Annotation(target.toNamed, tFire)
}

8
sim/midas/src/main/scala/midas/passes/fame/FAMETransform.scala
View File

@ -144,7 +144,7 @@ object FAMEModuleTransformer {
val gateTargetClock = analysis.containsSyncBlackboxes(m)
val targetClock = if (gateTargetClock) {
val buf = InstanceInfo(DefineAbstractClockGate.blackbox).connect("I", WRef(hostClock)).connect("CE", WRef(finishing))
SignalInfo(buf.decl, buf.assigns, WSubField(buf.ref, "O", ClockType, MALE))
SignalInfo(buf.decl, buf.assigns, WSubField(buf.ref, "O", ClockType, SourceFlow))
} else {
PassThru(WRef(hostClock), "target_clock")
}
@ -181,11 +181,11 @@ object FAMEModuleTransformer {
// Step 4: Replace refs and gate state updates
def onExpr(expr: Expression): Expression = expr.map(onExpr) match {
case iWR @ WRef(name, tpe, PortKind, MALE) if tpe != ClockType =>
// Generally MALE references to ports will be input channels, but RTL may use
case iWR @ WRef(name, tpe, PortKind, SourceFlow) if tpe != ClockType =>
// Generally SourceFlow references to ports will be input channels, but RTL may use
// an assignment to an output port as something akin to a wire, so check output ports too.
inChannelMap.getOrElse(name, outChannelMap(name)).replacePortRef(iWR)
case oWR @ WRef(name, tpe, PortKind, FEMALE) if tpe != ClockType =>
case oWR @ WRef(name, tpe, PortKind, SinkFlow) if tpe != ClockType =>
outChannelMap(name).replacePortRef(oWR)
case wr: WRef if wr.name == hostClock.name =>
// Replace host clock references with target clock references

2
sim/midas/src/main/scala/midas/passes/fame/JsonProtocol.scala
View File

@ -75,7 +75,7 @@ object JsonProtocol {
case e: org.json4s.ParserUtil.ParseException =>
Failure(new InvalidAnnotationJSONException(e.getMessage))
}.recoverWith { // If the input is a file, wrap in InvalidAnnotationFileException
case e => in match {
case e: firrtl.FirrtlUserException => in match {
case FileInput(file) =>
Failure(new InvalidAnnotationFileException(file, e))
case _ => Failure(e)

2
sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala
View File

@ -28,7 +28,7 @@ class GoldenGateCompilerPhase extends Phase with ConfigLookup {
val targetDir = annotations.collectFirst({ case TargetDirAnnotation(targetDir) => new File(targetDir) }).get
val configPackage = annotations.collectFirst({ case ConfigPackageAnnotation(p) => p }).get
val configString = annotations.collectFirst({ case ConfigStringAnnotation(s) => s }).get
val pNames = ParsedInputNames("UNUSED", "UNUSED", "UNUSED", configPackage, configString)
val pNames = ParsedInputNames("UNUSED", "UNUSED", "UNUSED", configPackage, configString, None)
val midasAnnos = Seq(InferReadWriteAnnotation)

2
sim/midas/src/main/scala/midas/stage/RuntimeConfigGenerationPhase.scala
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@ -21,7 +21,7 @@ class RuntimeConfigGenerationPhase extends Phase with ConfigLookup {
val configString = annotations.collectFirst({ case ConfigStringAnnotation(s) => s }).get
val runtimeConfigName = annotations.collectFirst({ case RuntimeConfigNameAnnotation(s) => s }).get
val pNames = ParsedInputNames("UNUSED", "UNUSED", "UNUSED", configPackage, configString)
val pNames = ParsedInputNames("UNUSED", "UNUSED", "UNUSED", configPackage, configString, None)
implicit val p = getParameters(pNames).alterPartial({
case OutputDir => targetDir

4
sim/midas/src/main/scala/midas/widgets/HostPort.scala
View File

@ -76,7 +76,7 @@ class HostPortIO[+T <: Data](protected val targetPortProto: T) extends Tokenized
field.valid := fwdChPort.bits.valid
revChPort.bits := field.ready
import chisel3.core.ExplicitCompileOptions.NotStrict
import chisel3.ExplicitCompileOptions.NotStrict
field.bits := fwdChPort.bits.bits
fromHostChannels += revChPort
@ -88,7 +88,7 @@ class HostPortIO[+T <: Data](protected val targetPortProto: T) extends Tokenized
fwdChPort.bits.valid := field.valid
field.ready := revChPort.bits
import chisel3.core.ExplicitCompileOptions.NotStrict
import chisel3.ExplicitCompileOptions.NotStrict
fwdChPort.bits.bits := field.bits
fromHostChannels += fwdChPort
toHostChannels += revChPort

2
sim/midas/src/main/scala/midas/widgets/Lib.scala
View File

@ -122,7 +122,7 @@ class MultiQueue[T <: Data](
// Rely on the ROB & freelist to ensure we are always enq-ing to an available
// slot
val ram = SeqMem(entries * numQueues, gen)
val ram = SyncReadMem(entries * numQueues, gen)
val enqPtrs = RegInit(VecInit(Seq.fill(numQueues)(0.U(log2Up(entries).W))))
val deqPtrs = RegInit(VecInit(Seq.fill(numQueues)(0.U(log2Up(entries).W))))
val maybe_full = RegInit(VecInit(Seq.fill(numQueues)(false.B)))

2
sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala
View File

@ -204,7 +204,7 @@ class PeekPokeTargetIO(targetIO: Seq[(String, Data)], withReset: Boolean) extend
val reset = if (withReset) Some(Output(Bool())) else None
override val elements = ListMap((
reset.map("reset" -> _).toSeq ++
targetIO.map({ case (name, field) => name -> Flipped(field.chiselCloneType) })
targetIO.map({ case (name, field) => name -> Flipped(chiselTypeOf(field)) })
):_*)
override def cloneType = new PeekPokeTargetIO(targetIO, withReset).asInstanceOf[this.type]
}

1
sim/midas/src/main/scala/midas/widgets/Widget.scala
View File

@ -5,7 +5,6 @@ package widgets
import chisel3._
import chisel3.util._
import chisel3.experimental.{MultiIOModule}
import chisel3.core.ActualDirection
import chisel3.core.DataMirror.directionOf
import junctions._

2
sim/midas/src/main/scala/strober/core/DaisyChain.scala
View File

@ -198,7 +198,7 @@ class SRAMChainControlIO(implicit override val p: Parameters)
class SRAMChainControl(implicit override val p: Parameters)
extends DaisyChainModule()(p) with SRAMChainParameters {
val io = IO(new SRAMChainControlIO)
val s_IDLE :: s_ADDRGEN :: s_MEMREAD :: s_DONE :: Nil = Enum(UInt(), 4)
val s_IDLE :: s_ADDRGEN :: s_MEMREAD :: s_DONE :: Nil = Enum(4)
val addrState = RegInit(s_IDLE)
val addrIns = Seq.fill(n)(Reg(UInt(w.W)))
val addrOut = Reg(UInt(w.W))

10
sim/midas/src/main/scala/strober/core/TraceQueue.scala
View File

@ -16,7 +16,7 @@ class TraceQueueIO[T <: Data](data: T, val entries: Int) extends Bundle {
}
class TraceQueue[T <: Data](data: T)(implicit p: Parameters) extends Module {
import Chisel._ // FIXME: due to a bug in SyncReadMem
//import Chisel._ // FIXME: due to a bug in SyncReadMem
val io = IO(new TraceQueueIO(data, p(TraceMaxLen)))
val do_flow = Wire(Bool())
@ -24,8 +24,8 @@ class TraceQueue[T <: Data](data: T)(implicit p: Parameters) extends Module {
val do_deq = io.deq.fire() && !do_flow
val maybe_full = RegInit(false.B)
val enq_ptr = RegInit(UInt(0, log2Ceil(io.entries)))
val deq_ptr = RegInit(UInt(0, log2Ceil(io.entries)))
val enq_ptr = RegInit(0.U(log2Ceil(io.entries).W))
val deq_ptr = RegInit(0.U(log2Ceil(io.entries).W))
val enq_wrap = enq_ptr === (io.limit - 2.U)
val deq_wrap = deq_ptr === (io.limit - 2.U)
when (do_enq) { enq_ptr := Mux(enq_wrap, 0.U, enq_ptr + 1.U) }
@ -38,7 +38,7 @@ class TraceQueue[T <: Data](data: T)(implicit p: Parameters) extends Module {
val atLeastTwo = full || enq_ptr - deq_ptr >= 2.U
do_flow := empty && io.deq.ready
val ram = SyncReadMem(io.entries, data.chiselCloneType)
val ram = SyncReadMem(io.entries, chiselTypeOf(data))
when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
@ -71,7 +71,7 @@ object TraceQueue {
val trace = Queue(queue.io.deq, 1, pipe=true)
// for debugging
val count = RegInit(UInt(0, 32))
val count = RegInit(0.U(32.W))
count suggestName s"${name}_count"
when (trace.fire() =/= queue.io.enq.fire()) {
count := Mux(trace.fire(), count - 1.U, count + 1.U)

2
sim/midas/targetutils/src/main/scala/midas/annotations.scala
View File

@ -3,7 +3,7 @@
package midas.targetutils
import chisel3._
import chisel3.experimental.{BaseModule, ChiselAnnotation, dontTouch}
import chisel3.experimental.{BaseModule, ChiselAnnotation}
import firrtl.{RenameMap}
import firrtl.annotations.{NoTargetAnnotation, SingleTargetAnnotation, ComponentName} // Deprecated

6
sim/src/main/makefrag/firesim/Makefrag
View File

@ -33,7 +33,11 @@ HEADER := $(GENERATED_DIR)/$(DESIGN)-const.h
common_chisel_args = $(patsubst $(base_dir)/%,%,$(GENERATED_DIR)) $(DESIGN_PACKAGE) $(DESIGN) $(TARGET_CONFIG_PACKAGE) $(TARGET_CONFIG) $(PLATFORM_CONFIG_PACKAGE) $(PLATFORM_CONFIG)
ifdef FIRESIM_STANDALONE
firesim_sbt_project := {file:${firesim_base_dir}/target-rtl/chipyard/}firechip
firesim_sbt_project := {file:${chipyard_dir}}firechip
lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.scala" -print 2> /dev/null)
SOURCE_DIRS = $(chipyard_dir)/generators $(firesim_base_dir)
SCALA_SOURCES = $(call lookup_scala_srcs,$(SOURCE_DIRS))
else
firesim_sbt_project := firechip
endif

1
sim/src/main/scala/fasedtests/AXI4Fuzzer.scala
View File

@ -3,7 +3,6 @@
package firesim.fasedtests
import chisel3._
import chisel3.experimental.{RawModule, MultiIOModule}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.amba.axi4._

2
sim/src/main/scala/midasexamples/GCD.scala
View File

@ -4,7 +4,7 @@ package firesim.midasexamples
import chisel3._
import chisel3.util.unless
import chisel3.experimental.{withClock, RawModule}
import chisel3.experimental.{withClock}
import midas.widgets.PeekPokeBridge

2
sim/src/main/scala/midasexamples/Parity.scala
View File

@ -10,7 +10,7 @@ class ParityDUT extends Module {
val in = Input(Bool())
val out = Output(Bool())
})
val s_even :: s_odd :: Nil = Enum(UInt(), 2)
val s_even :: s_odd :: Nil = Enum(2)
val state = RegInit(s_even)
when (io.in) {
when (state === s_even) { state := s_odd }

2
sim/src/main/scala/midasexamples/PointerChaser.scala
View File

@ -4,7 +4,7 @@ package firesim.midasexamples
import chisel3._
import chisel3.util._
import chisel3.experimental.{withClock, RawModule}
import chisel3.experimental.{withClock}
import junctions._
import freechips.rocketchip.config.{Parameters, Field}

1
sim/src/main/scala/midasexamples/PrintfModule.scala
View File

@ -4,7 +4,6 @@ package firesim.midasexamples
import chisel3._
import chisel3.util.LFSR16
import chisel3.experimental.MultiIOModule
import midas.targetutils.SynthesizePrintf

2
sim/src/main/scala/midasexamples/Risc.scala
View File

@ -18,7 +18,7 @@ class RiscDUT extends Module {
val code = Mem(256, UInt(32.W))
val pc = RegInit(0.U(8.W))
val add_op :: imm_op :: Nil = Enum(UInt(), 2)
val add_op :: imm_op :: Nil = Enum(2)
val inst = code(pc)
val op = inst(31,24)

8
sim/src/main/scala/midasexamples/RiscSRAM.scala
View File

@ -15,16 +15,16 @@ class RiscSRAMDUT extends Module {
val valid = Output(Bool())
val out = Output(UInt(32.W))
})
val fileMem = SeqMem(256, UInt(32.W))
val fileMem = SyncReadMem(256, UInt(32.W))
// We only support combinational mems for now
//chisel3.experimental.annotate(MemModelAnnotation(fileMem))
val codeMem = SeqMem(128, UInt(32.W))
val codeMem = SyncReadMem(128, UInt(32.W))
//chisel3.experimental.annotate(MemModelAnnotation(codeMem))
val idle :: fetch :: decode :: ra_read :: rb_read :: rc_write :: Nil = Enum(UInt(), 6)
val idle :: fetch :: decode :: ra_read :: rb_read :: rc_write :: Nil = Enum(6)
val state = RegInit(idle)
val add_op :: imm_op :: Nil = Enum(UInt(), 2)
val add_op :: imm_op :: Nil = Enum(2)
val pc = RegInit(0.U(8.W))
val raData = Reg(UInt(32.W))
val rbData = Reg(UInt(32.W))

2
sim/src/main/scala/midasexamples/Util.scala
View File

@ -3,7 +3,7 @@
package firesim.midasexamples
import chisel3._
import chisel3.experimental.{withClock, RawModule}
import chisel3.experimental.{withClock}
import midas.widgets.PeekPokeBridge

2
sim/src/main/scala/midasexamples/VerilogAccumulator.scala
View File

@ -4,7 +4,7 @@ package firesim.midasexamples
import chisel3._
import chisel3.util.{unless, HasBlackBoxInline}
import chisel3.experimental.{withClockAndReset, RawModule}
import chisel3.experimental.{withClockAndReset}
import midas.widgets.PeekPokeBridge

1
sim/src/main/scala/midasexamples/WireInterconnect.scala
View File

@ -5,7 +5,6 @@ package firesim.midasexamples
import chisel3._
import chisel3.util._
import chisel3.experimental.MultiIOModule
class PipeModule[T <: Data](gen: T, latency: Int = 0) extends MultiIOModule {
val in = IO(Input(gen))

2
target-design/chipyard

@ -1 +1 @@
Subproject commit e859fb1779eccf70cc9fd095b3fd2e6daf667600
Subproject commit 86a473dbf6e596d092d57e9c199bca053020f326