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passes asm tests (does not exclude boom yet, see next commit)

This commit is contained in:
Sagar Karandikar 2018-09-26 20:47:41 +00:00
parent 9ca200cc03
commit a3c354c9e5
5 changed files with 7 additions and 7 deletions
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4
sim/build.sbt
View File

@ -15,7 +15,7 @@ lazy val commonSettings = Seq(
)
lazy val rocketchip = RootProject(file("target-rtl/firechip/rocket-chip"))
lazy val boom = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
//lazy val boom = project in file("target-rtl/firechip/boom") settings commonSettings dependsOn rocketchip
lazy val sifiveip = project in file("target-rtl/firechip/sifive-blocks") settings commonSettings dependsOn rocketchip
lazy val testchipip = project in file("target-rtl/firechip/testchipip") settings commonSettings dependsOn rocketchip
lazy val icenet = project in file("target-rtl/firechip/icenet") settings commonSettings dependsOn (rocketchip, testchipip)
@ -24,4 +24,4 @@ lazy val mdf = RootProject(file("barstools/mdf/scalalib"))
lazy val barstools = project in file("barstools/macros") settings commonSettings dependsOn (mdf, rocketchip)
lazy val midas = project in file("midas") settings commonSettings dependsOn barstools
lazy val firesim = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet, boom)
lazy val firesim = project in file(".") settings commonSettings dependsOn (midas, sifiveip, testchipip, icenet/*, boom*/)

2
sim/firrtl

@ -1 +1 @@
Subproject commit b7ea6329716bb978a1953fd65a391cb76e045e0d
Subproject commit ba12915e9b93685107c503b3f91b96d491c48459

2
sim/midas

@ -1 +1 @@
Subproject commit 3ef827ec358f4431f3764c4022086fc19b70ea08
Subproject commit 6e2a15223481f7ff267d14a47c4ffccc5f082818

4
sim/src/main/scala/firesim/Targets.scala
View File

@ -25,7 +25,7 @@ import java.io.File
class FireSim(implicit p: Parameters) extends RocketSubsystem
with CanHaveMisalignedMasterAXI4MemPort
with HasPeripheryBootROM
with HasSystemErrorSlave
// with HasSystemErrorSlave
// with HasSyncExtInterrupts
with HasNoDebug
with HasPeripherySerial
@ -50,7 +50,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
with CanHaveMisalignedMasterAXI4MemPort
with HasPeripheryBootROM
with HasSystemErrorSlave
// with HasSystemErrorSlave
// with HasSyncExtInterrupts
with HasNoDebug
with HasPeripherySerial

2
target-design/firechip

@ -1 +1 @@
Subproject commit dc2509f3b72bc73410e3e493dd344dbebdddfcef
Subproject commit b9e70a36c203466b0e4521b7882e5c0e61c8d85c