Continue to copy AXI4M traits due to type-system challenges
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David Biancolin
parent
db94bdc244
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a283512ff7
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@ -38,9 +38,11 @@ trait HasDefaultBusConfiguration {
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}
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/** Adds a port to the system intended to master an AXI4 DRAM controller. */
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trait CanHaveMisalignedMasterAXI4MemPort { this: BaseSubsystem =>
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val module: CanHaveMisalignedMasterAXI4MemPortModuleImp
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/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
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* associated with each port. This drives FASED functional model sizing
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*/
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trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem =>
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val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
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val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) =>
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val portName = "axi4"
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@ -71,8 +73,8 @@ trait CanHaveMisalignedMasterAXI4MemPort { this: BaseSubsystem =>
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}
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/** Actually generates the corresponding IO in the concrete Module */
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trait CanHaveMisalignedMasterAXI4MemPortModuleImp extends LazyModuleImp {
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val outer: CanHaveMisalignedMasterAXI4MemPort
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trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp {
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val outer: CanHaveFASEDOptimizedMasterAXI4MemPort
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val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in))))
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(mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) =>
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@ -89,18 +91,6 @@ trait CanHaveMisalignedMasterAXI4MemPortModuleImp extends LazyModuleImp {
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}
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}
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///* Deploy once we bump to RC's misaligned support */
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//trait CanHaveFASEDCompatibleAXI4MemPortModuleImp extends CanHaveMasterAXI4MemPortModuleImp {
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// val outer: CanHaveMasterAXI4MemPort
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//
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// // :nohacks: JANK :nohacks:---------- --------------V
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// override val mem_axi4 = outer.memAXI4Node.map(x => Wire(HeterogeneousBag.fromNode(x.in)))
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//
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// val mem_axi4_with_edge = outer.memAXI4Node.map(n => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(n.in))))
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// mem_axi4_with_edge.get <> mem_axi4.get
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//
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//}
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/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
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* TracerV endpoint can match on.
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*/
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@ -32,7 +32,7 @@ import java.io.File
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class FireSim(implicit p: Parameters) extends RocketSubsystem
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with HasDefaultBusConfiguration
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with CanHaveMisalignedMasterAXI4MemPort
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with CanHaveFASEDOptimizedMasterAXI4MemPort
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with HasPeripheryBootROM
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with HasNoDebug
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with HasPeripherySerial
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@ -46,7 +46,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem
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class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
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with HasRTCModuleImp
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with CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
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with HasPeripheryBootROMModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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@ -58,7 +58,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
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class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
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with HasDefaultBusConfiguration
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with CanHaveMisalignedMasterAXI4MemPort
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with CanHaveFASEDOptimizedMasterAXI4MemPort
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with HasPeripheryBootROM
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with HasNoDebug
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with HasPeripherySerial
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@ -71,7 +71,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
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class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l)
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with HasRTCModuleImp
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with CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
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with HasPeripheryBootROMModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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@ -82,7 +82,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
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class FireBoom(implicit p: Parameters) extends BoomSubsystem
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with HasDefaultBusConfiguration
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with CanHaveMisalignedMasterAXI4MemPort
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with CanHaveFASEDOptimizedMasterAXI4MemPort
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with HasPeripheryBootROM
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with HasNoDebug
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with HasPeripherySerial
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@ -96,7 +96,7 @@ class FireBoom(implicit p: Parameters) extends BoomSubsystem
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class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l)
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with HasRTCModuleImp
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with CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
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with HasPeripheryBootROMModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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@ -107,7 +107,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l)
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class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem
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with HasDefaultBusConfiguration
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with CanHaveMisalignedMasterAXI4MemPort
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with CanHaveFASEDOptimizedMasterAXI4MemPort
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with HasPeripheryBootROM
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with HasNoDebug
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with HasPeripherySerial
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@ -120,7 +120,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem
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class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemModuleImp(l)
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with HasRTCModuleImp
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with CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
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with HasPeripheryBootROMModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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