Removed the clock bridge annotation (#1224)

Removed the specialised clock bridge annotation to fully re-use the
functionality provided by the serializable bridge annotation.
Pattern matching now needs to verify the widget constructor name.

sim/midas/src/main/scala/midas/passes/ExtractBridges.scala

@@ -2,7 +2,7 @@
 
 package midas.passes
 
-import midas.widgets.{BridgeAnnotation, ClockBridgeAnnotation}
+import midas.widgets.{BridgeAnnotation, ClockBridgeModule}
 import midas.passes.fame.{PromoteSubmodule, PromoteSubmoduleAnnotation, FAMEChannelConnectionAnnotation}
 
 import firrtl._
@@ -100,8 +100,9 @@ private[passes] class BridgeExtraction extends firrtl.Transform {
     topModule.foreach(getBridgeConnectivity(portInstPairs, instList))
     val instMap = instList.toMap
 
-    val clockBridgeInsts = instList.map(inst => inst._1 -> bridgeAnnoMap(instMap(inst._1)))
-                              .collect({ case (inst, cb: ClockBridgeAnnotation) => inst })
+    val clockBridgeInsts = instList
+        .map(inst => inst._1 -> bridgeAnnoMap(instMap(inst._1)))
+        .collect({ case (inst, cb: BridgeAnnotation) if cb.widgetClass == classOf[ClockBridgeModule].getName => inst })
 
     val bridgeInstMessage = "You must use a single ClockBridge instance to generate clocks for your simulated system."
     assert(clockBridgeInsts.nonEmpty, s"No ClockBridge instances found. ${bridgeInstMessage}")

sim/midas/src/main/scala/midas/widgets/Bridge.scala

@@ -61,7 +61,7 @@ trait Bridge[HPType <: Record with HasChannels, WidgetType <: BridgeModule[HPTyp
 
     // Generate the bridge annotation
     annotate(new ChiselAnnotation { def toFirrtl = {
-        SerializableBridgeAnnotation(
+        BridgeAnnotation(
           self.toNamed.toTarget,
           bridgeIO.allChannelNames,
           widgetClass = widgetClassSymbol.fullName,

sim/midas/src/main/scala/midas/widgets/BridgeAnnotations.scala

@@ -9,22 +9,14 @@ import freechips.rocketchip.config.Parameters
 
 import midas.targetutils.FAMEAnnotation
 
-trait BridgeAnnotation extends SingleTargetAnnotation[ModuleTarget] {
-  // A list of channel names that match the globalName emitted in the FCCAs
-  // associated with this bridge. We use these strings to look up those annotations
-  def channelNames: Seq[String]
-  // Invoked by BridgeExtraction to convert this ModuleTarget-based annotation into
-  // a ReferenceTarget based one that can be attached to newly created IO on the top-level
-  def toIOAnnotation(port: String): BridgeIOAnnotation
-}
 
 /**
-  * A serializable form of BridgeAnnotation emitted by Chisel Modules that extend Bridge
+  * A serializable annotation emitted by Chisel Modules that extend Bridge
   *
   * @param target  The module representing an Bridge. Typically a black box
   *
-  * @param channelNames  See BridgeAnnotation. A list of channelNames used
-  *  to find associated FCCAs for this bridge
+  * @param channelNames  A list of channel names that match the globalName emitted in the FCCAs
+  *   associated with this bridge. We use these strings to look up those annotations
   *
   * @param widgetClass  The full class name of the BridgeModule generator
   *
@@ -37,20 +29,17 @@ trait BridgeAnnotation extends SingleTargetAnnotation[ModuleTarget] {
   *   additional pertinent classes
   */
 
-case class SerializableBridgeAnnotation[T <: AnyRef](
+case class BridgeAnnotation(
     target: ModuleTarget,
     channelNames: Seq[String],
     widgetClass: String,
-    widgetConstructorKey: Option[T])
-  extends BridgeAnnotation with HasSerializationHints with FAMEAnnotation {
+    widgetConstructorKey: Option[_ <: AnyRef])
+  extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation with HasSerializationHints {
 
-  def typeHints() = widgetConstructorKey match {
-    // If the key has extra type hints too, grab them as well
-    case Some(key: HasSerializationHints) => key.getClass +: key.typeHints
-    case Some(key) => Seq(key.getClass)
-    case None => Seq()
-  }
-  def duplicate(n: ModuleTarget) = this.copy(target)
+  /**
+    * Invoked by BridgeExtraction to convert this ModuleTarget-based annotation into
+    * a ReferenceTarget based one that can be attached to newly created IO on the top-level
+    */
   def toIOAnnotation(port: String): BridgeIOAnnotation = {
     val channelMapping = channelNames.map(oldName => oldName -> s"${port}_$oldName")
     BridgeIOAnnotation(target.copy(module = target.circuit).ref(port),
@@ -58,6 +47,15 @@ case class SerializableBridgeAnnotation[T <: AnyRef](
       widgetClass = widgetClass,
       widgetConstructorKey = widgetConstructorKey)
   }
+
+  def typeHints() = widgetConstructorKey match {
+    // If the key has extra type hints too, grab them as well
+    case Some(key: HasSerializationHints) => key.getClass +: key.typeHints
+    case Some(key) => Seq(key.getClass)
+    case None => Seq()
+  }
+
+  def duplicate(n: ModuleTarget) = this.copy(target)
 }
 
 /**
@@ -72,7 +70,7 @@ case class SerializableBridgeAnnotation[T <: AnyRef](
   * @param clockInfo Contains information about the domain in which the bridge is instantiated. 
   *  This will always be nonEmpty for bridges instantiated in the input FIRRTL
   *
-  * @param widgetClass The BridgeModule's full class name. See SerializableBridgeAnnotation
+  * @param widgetClass The BridgeModule's full class name. See BridgeAnnotation
   *
   * @param widgetConstructorKey The BridgeModule's constructor argument.
   *

sim/midas/src/main/scala/midas/widgets/ClockBridge.scala

@@ -55,30 +55,6 @@ object FindScaledPeriodGCD {
   }
 }
 
-/**
-  * A custom bridge annotation for the Clock Bridge. Unique so that we can
-  * trivially match against it in bridge extraction.
-  *
-  * @param target The target-side module for the CB
-  *
-  * @param clocks The associated clock information for each output clock
-  *
-  */
-
-case class ClockBridgeAnnotation(val target: ModuleTarget, clocks: Seq[RationalClock])
-    extends BridgeAnnotation with ClockBridgeConsts {
-  val channelNames = Seq(clockChannelName)
-  def duplicate(n: ModuleTarget) = this.copy(target)
-  def toIOAnnotation(port: String): BridgeIOAnnotation = {
-    val channelMapping = channelNames.map(oldName => oldName -> s"${port}_$oldName")
-    BridgeIOAnnotation(
-      target.copy(module = target.circuit).ref(port),
-      channelMapping.toMap,
-      widgetClass = classOf[ClockBridgeModule].getName,
-      widgetConstructorKey = Some(ClockParameters(clocks)))
-  }
-}
-
 /**
  * Parameters to construct a clock bridge from. Aggregates information about all the output clocks.
  *
@@ -108,7 +84,14 @@ class RationalClockBridge(val allClocks: Seq[RationalClock]) extends BlackBox wi
   val clockMFMRs = scaledPeriods.map { period => ((period + (minPeriod - 1)) / minPeriod).toInt }
 
   // Generate the bridge annotation
-  annotate(new ChiselAnnotation { def toFirrtl = ClockBridgeAnnotation(outer.toTarget, allClocks) })
+  annotate(new ChiselAnnotation { def toFirrtl =
+      BridgeAnnotation(
+        target = outer.toTarget,
+        channelNames = Seq(clockChannelName),
+        widgetClass = classOf[ClockBridgeModule].getName,
+        widgetConstructorKey = Some(ClockParameters(allClocks))
+      )
+  })
   annotate(new ChiselAnnotation { def toFirrtl =
       FAMEChannelConnectionAnnotation(
         clockChannelName,