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Merge pull request #1500 from firesim/renameserial 

Rename SerialBridge to TSIBridge
This commit is contained in:
Jerry Zhao 2023-05-10 11:37:26 -07:00 committed by GitHub
parent 0c1a7a6339 73ad11a969
commit 966e09907c
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 65 additions and 66 deletions
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2
docs/Golden-Gate/Bridges.rst
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@ -11,7 +11,7 @@ Bridges enable:
Here you instantiate bridges at the I/O boundary of your chip, to provide
a simulation models of the environment your design is executing in. For an
FPGA-hosted model, see FASED memory timing models. For co-simulated models
see the UARTBridge, BlockDeviceBridge, and SerialBridge.
see the UARTBridge, BlockDeviceBridge, and TSIBridge.
#. **Verification against a software golden model.** Attach an bridge (anywhere
in your target RTL) to an interface you'd like to monitor, (e.g., a

2
sim/.scalafmt.conf
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@ -9,7 +9,7 @@ project {
"glob:**firesim-lib/src/main/scala/bridges/BlockDevBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/DromajoBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/GroundTestBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/SerialBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/TSIBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/SimpleNICBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/TracerVBridge.scala",
"glob:**firesim-lib/src/main/scala/bridges/UARTBridge.scala",

46
sim/firesim-lib/src/main/cc/bridges/serial.cc → sim/firesim-lib/src/main/cc/bridges/tsibridge.cc
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@ -1,6 +1,6 @@
// See LICENSE for license details
#include "serial.h"
#include "tsibridge.h"
#include "bridges/loadmem.h"
#include "core/simif.h"
#include "fesvr/firesim_tsi.h"
@ -8,20 +8,20 @@
#include <cassert>
#include <gmp.h>
char serial_t::KIND;
char tsibridge_t::KIND;
serial_t::serial_t(simif_t &simif,
loadmem_t &loadmem_widget,
const SERIALBRIDGEMODULE_struct &mmio_addrs,
int serialno,
const std::vector<std::string> &args,
bool has_mem,
int64_t mem_host_offset)
tsibridge_t::tsibridge_t(simif_t &simif,
loadmem_t &loadmem_widget,
const TSIBRIDGEMODULE_struct &mmio_addrs,
int tsino,
const std::vector<std::string> &args,
bool has_mem,
int64_t mem_host_offset)
: bridge_driver_t(simif, &KIND), mmio_addrs(mmio_addrs),
loadmem_widget(loadmem_widget), has_mem(has_mem),
mem_host_offset(mem_host_offset) {
std::string num_equals = std::to_string(serialno) + std::string("=");
std::string num_equals = std::to_string(tsino) + std::string("=");
std::string prog_arg = std::string("+prog") + num_equals;
std::vector<std::string> args_vec;
args_vec.push_back("firesim_tsi");
@ -56,7 +56,7 @@ serial_t::serial_t(simif_t &simif,
}
// debug for command line arguments
printf("command line for program %d. argc=%d:\n", serialno, argc_count);
printf("command line for program %d. argc=%d:\n", tsino, argc_count);
for (int i = 0; i < argc_count; i++) {
printf("%s ", tsi_argv[i + 1]);
}
@ -65,7 +65,7 @@ serial_t::serial_t(simif_t &simif,
tsi_argc = argc_count + 1;
}
serial_t::~serial_t() {
tsibridge_t::~tsibridge_t() {
delete fesvr;
if (tsi_argv) {
for (int i = 0; i < tsi_argc; ++i) {
@ -75,7 +75,7 @@ serial_t::~serial_t() {
}
}
void serial_t::init() {
void tsibridge_t::init() {
// `ucontext` used by tsi cannot be created in one thread and resumed in
// another. To ensure that the tsi process is on the correct thread, it is
// built here, as the bridge constructor may be invoked from a thread other
@ -85,23 +85,23 @@ void serial_t::init() {
go();
}
void serial_t::go() { write(mmio_addrs.start, 1); }
void tsibridge_t::go() { write(mmio_addrs.start, 1); }
void serial_t::send() {
void tsibridge_t::send() {
while (fesvr->data_available() && read(mmio_addrs.in_ready)) {
write(mmio_addrs.in_bits, fesvr->recv_word());
write(mmio_addrs.in_valid, 1);
}
}
void serial_t::recv() {
void tsibridge_t::recv() {
while (read(mmio_addrs.out_valid)) {
fesvr->send_word(read(mmio_addrs.out_bits));
write(mmio_addrs.out_ready, 1);
}
}
void serial_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
void tsibridge_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
assert(loadmem.size % sizeof(uint32_t) == 0);
assert(has_mem);
// Loadmem reads are in granularities of the width of the FPGA-DRAM bus
@ -133,7 +133,7 @@ void serial_t::handle_loadmem_read(firesim_loadmem_t loadmem) {
fesvr->tick();
}
void serial_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
void tsibridge_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
assert(loadmem.size <= 1024);
assert(has_mem);
static char buf[1024];
@ -152,7 +152,7 @@ void serial_t::handle_loadmem_write(firesim_loadmem_t loadmem) {
mpz_clear(data);
}
void serial_t::serial_bypass_via_loadmem() {
void tsibridge_t::tsi_bypass_via_loadmem() {
firesim_loadmem_t loadmem;
while (fesvr->has_loadmem_reqs()) {
// Check for reads first as they preceed a narrow write;
@ -163,7 +163,7 @@ void serial_t::serial_bypass_via_loadmem() {
}
}
void serial_t::tick() {
void tsibridge_t::tick() {
// First, check to see step_size tokens have been enqueued
if (!read(mmio_addrs.done))
return;
@ -174,7 +174,7 @@ void serial_t::tick() {
fesvr->tick();
}
if (fesvr->has_loadmem_reqs()) {
serial_bypass_via_loadmem();
tsi_bypass_via_loadmem();
}
if (!terminate()) {
// Write all the requests to the target
@ -183,5 +183,5 @@ void serial_t::tick() {
}
}
bool serial_t::terminate() { return fesvr->done(); }
int serial_t::exit_code() { return fesvr->exit_code(); }
bool tsibridge_t::terminate() { return fesvr->done(); }
int tsibridge_t::exit_code() { return fesvr->exit_code(); }

30
sim/firesim-lib/src/main/cc/bridges/serial.h → sim/firesim-lib/src/main/cc/bridges/tsibridge.h
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@ -1,6 +1,6 @@
// See LICENSE for license details
#ifndef __SERIAL_H
#define __SERIAL_H
#ifndef __TSIBRIDGE_H
#define __TSIBRIDGE_H
#include "bridges/serial_data.h"
#include "core/bridge_driver.h"
@ -9,7 +9,7 @@ class loadmem_t;
class firesim_tsi_t;
class firesim_loadmem_t;
struct SERIALBRIDGEMODULE_struct {
struct TSIBRIDGEMODULE_struct {
uint64_t in_bits;
uint64_t in_valid;
uint64_t in_ready;
@ -21,26 +21,26 @@ struct SERIALBRIDGEMODULE_struct {
uint64_t start;
};
class serial_t : public bridge_driver_t {
class tsibridge_t : public bridge_driver_t {
public:
/// The identifier for the bridge type used for casts.
static char KIND;
serial_t(simif_t &simif,
loadmem_t &loadmem_widget,
const SERIALBRIDGEMODULE_struct &mmio_addrs,
int serialno,
const std::vector<std::string> &args,
bool has_mem,
int64_t mem_host_offset);
~serial_t();
tsibridge_t(simif_t &simif,
loadmem_t &loadmem_widget,
const TSIBRIDGEMODULE_struct &mmio_addrs,
int tsino,
const std::vector<std::string> &args,
bool has_mem,
int64_t mem_host_offset);
~tsibridge_t();
virtual void init();
virtual void tick();
virtual bool terminate();
virtual int exit_code();
private:
const SERIALBRIDGEMODULE_struct mmio_addrs;
const TSIBRIDGEMODULE_struct mmio_addrs;
loadmem_t &loadmem_widget;
firesim_tsi_t *fesvr;
@ -63,7 +63,7 @@ private:
// Helper functions to handoff fesvr requests to the loadmem unit
void handle_loadmem_read(firesim_loadmem_t loadmem);
void handle_loadmem_write(firesim_loadmem_t loadmem);
void serial_bypass_via_loadmem();
void tsi_bypass_via_loadmem();
};
#endif // __SERIAL_H
#endif // __TSIBRIDGE_H

45
sim/firesim-lib/src/main/scala/bridges/SerialBridge.scala → sim/firesim-lib/src/main/scala/bridges/TSIBridge.scala
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@ -7,53 +7,52 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import testchipip.{SerialIO, SerialAdapter}
import testchipip.{TSIIO, TSI}
/**
* Class which parameterizes the SerialBridge
* Class which parameterizes the TSIBridge
*
* memoryRegionNameOpt, if unset, indicates that firesim-fesvr should not attempt to write a payload into DRAM through the loadmem unit.
* This is suitable for target designs which do not use the FASED DRAM model.
* If a FASEDBridge for the backing AXI4 memory is present, then memoryRegionNameOpt should be set to the same memory region name which is passed
* to the FASEDBridge. This enables fast payload loading in firesim-fesvr through the loadmem unit.
*/
case class SerialBridgeParams(memoryRegionNameOpt: Option[String])
case class TSIBridgeParams(memoryRegionNameOpt: Option[String])
class SerialBridge(memoryRegionNameOpt: Option[String]) extends BlackBox with Bridge[HostPortIO[SerialBridgeTargetIO], SerialBridgeModule] {
val io = IO(new SerialBridgeTargetIO)
class TSIBridge(memoryRegionNameOpt: Option[String]) extends BlackBox with Bridge[HostPortIO[TSIBridgeTargetIO], TSIBridgeModule] {
val io = IO(new TSIBridgeTargetIO)
val bridgeIO = HostPort(io)
val constructorArg = Some(SerialBridgeParams(memoryRegionNameOpt))
val constructorArg = Some(TSIBridgeParams(memoryRegionNameOpt))
generateAnnotations()
}
object SerialBridge {
def apply(clock: Clock, port: SerialIO, memoryRegionNameOpt: Option[String], reset: Bool)(implicit p: Parameters): SerialBridge = {
val ep = Module(new SerialBridge(memoryRegionNameOpt))
ep.io.serial <> port
object TSIBridge {
def apply(clock: Clock, port: TSIIO, memoryRegionNameOpt: Option[String], reset: Bool)(implicit p: Parameters): TSIBridge = {
val ep = Module(new TSIBridge(memoryRegionNameOpt))
ep.io.tsi <> port
ep.io.clock := clock
ep.io.reset := reset
ep
}
}
class SerialBridgeTargetIO extends Bundle {
val serial = Flipped(new SerialIO(SerialAdapter.SERIAL_TSI_WIDTH))
class TSIBridgeTargetIO extends Bundle {
val tsi = Flipped(new TSIIO)
val reset = Input(Bool())
val clock = Input(Clock())
}
class SerialBridgeModule(serialBridgeParams: SerialBridgeParams)(implicit p: Parameters)
extends BridgeModule[HostPortIO[SerialBridgeTargetIO]]()(p) {
class TSIBridgeModule(tsiBridgeParams: TSIBridgeParams)(implicit p: Parameters)
extends BridgeModule[HostPortIO[TSIBridgeTargetIO]]()(p) {
lazy val module = new BridgeModuleImp(this) {
val io = IO(new WidgetIO)
val hPort = IO(HostPort(new SerialBridgeTargetIO))
val hPort = IO(HostPort(new TSIBridgeTargetIO))
val serialBits = SerialAdapter.SERIAL_TSI_WIDTH
val inBuf = Module(new Queue(UInt(serialBits.W), 16))
val outBuf = Module(new Queue(UInt(serialBits.W), 16))
val inBuf = Module(new Queue(UInt(TSI.WIDTH.W), 16))
val outBuf = Module(new Queue(UInt(TSI.WIDTH.W), 16))
val tokensToEnqueue = RegInit(0.U(32.W))
val target = hPort.hBits.serial
val target = hPort.hBits.tsi
val tFire = hPort.toHost.hValid && hPort.fromHost.hReady && tokensToEnqueue =/= 0.U
val targetReset = tFire & hPort.hBits.reset
inBuf.reset := reset.asBool || targetReset
@ -90,16 +89,16 @@ class SerialBridgeModule(serialBridgeParams: SerialBridgeParams)(implicit p: Par
genCRFile()
override def genHeader(base: BigInt, memoryRegions: Map[String, BigInt], sb: StringBuilder): Unit = {
val memoryRegionNameOpt = serialBridgeParams.memoryRegionNameOpt
val memoryRegionNameOpt = tsiBridgeParams.memoryRegionNameOpt
val offsetConst = memoryRegionNameOpt.map(memoryRegions(_)).getOrElse(BigInt(0))
genConstructor(
base,
sb,
"serial_t",
"serial",
"tsibridge_t",
"tsibridge",
Seq(
CppBoolean(serialBridgeParams.memoryRegionNameOpt.isDefined),
CppBoolean(tsiBridgeParams.memoryRegionNameOpt.isDefined),
UInt64(offsetConst)
),
hasLoadMem = true

2
sim/make/cpp-lint.mk
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@ -14,7 +14,7 @@ clang_tidy_files := $(shell \
| grep -v simif_ \
| grep -v tracerv \
| grep -v dromajo \
| grep -v serial \
| grep -v tsibridge \
| grep -v fesvr \
| grep -v generated-src \
| grep -v output \

2
sim/src/main/makefrag/bridges/driver.mk
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@ -17,7 +17,7 @@ DRIVER_CC := \
$(testchipip_csrc_dir)/testchip_tsi.cc \
$(wildcard $(addprefix $(firesim_lib_dir)/, \
bridges/uart.cc \
bridges/serial.cc \
bridges/tsibridge.cc \
bridges/blockdev.cc \
bridges/tracerv.cc \
fesvr/firesim_tsi.cc \

2
target-design/chipyard

@ -1 +1 @@
Subproject commit 3b303ba37d3a9f197ca1cb1b4865649f7b586cb8
Subproject commit eced8e63d9171d5b03c50ac1503ba54fa18ef002