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[docs] Update filenames in docs

This commit is contained in:
David Biancolin 2021-07-29 22:29:09 +00:00
parent 6789143b7c
commit 95881aac63
2 changed files with 8 additions and 8 deletions
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2
docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/Printf-Synthesis.rst
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@ -42,7 +42,7 @@ For example, if your previous ``PLATFORM_CONFIG`` was
``PLATFORM_CONFIG=WithPrintfSynthesis_BaseF1Config_F120MHz``. Notice that you ``PLATFORM_CONFIG=WithPrintfSynthesis_BaseF1Config_F120MHz``. Notice that you
must prepend the mixin (rather than appending). During compilation, Golden must prepend the mixin (rather than appending). During compilation, Golden
Gate will print the number of printfs it has synthesized. In the target's Gate will print the number of printfs it has synthesized. In the target's
generated header (``<DESIGN>-const.h``), you'll find metadata for each of the generated header (``FireSim-generated.const.h``), you'll find metadata for each of the
printfs Golden Gate synthesized. This is passed as argument to the constructor printfs Golden Gate synthesized. This is passed as argument to the constructor
of the ``synthesized_prints_t`` bridge driver, which will be automatically of the ``synthesized_prints_t`` bridge driver, which will be automatically
instantiated in FireSim driver. instantiated in FireSim driver.

14
docs/Golden-Gate/Output-Files.rst
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@ -11,20 +11,20 @@ Core Files
These are used in nearly all flows. These are used in nearly all flows.
* **<BASE>.v**: The verilog implementation of the simulator which will be synthesized onto the FPGA. The top-level is the Shim module specified in the ``PLATFORM_CONFIG``. * **<BASE>.v**: The verilog implementation of the simulator which will be synthesized onto the FPGA. The top-level is the Shim module specified in the ``PLATFORM_CONFIG``.
* **<BASE>_const.h**: A target-specific header containing all necessary metadata to instantiate bridge drivers. This is linked into the simulator driver and meta-simulators (FPGA-level / MIDAS-level). Often referred to as "the header". * **<BASE>.const.h**: A target-specific header containing all necessary metadata to instantiate bridge drivers. This is linked into the simulator driver and meta-simulators (FPGA-level / MIDAS-level). Often referred to as "the header".
* **<BASE>_runtime.conf**: Default plus args for generated FASED memory timing models. Most other bridges have their defaults baked into the driver. * **<BASE>.runtime.conf**: Default plus args for generated FASED memory timing models. Most other bridges have their defaults baked into the driver.
FPGA Synthesis Files FPGA Synthesis Files
------------------------------------- -------------------------------------
These are additional files passed to the FPGA build directory. These are additional files passed to the FPGA build directory.
* **<BASE>_defines.vh**: Verilog macro definitions for FPGA synthesis. * **<BASE>.defines.vh**: Verilog macro definitions for FPGA synthesis.
* **<BASE>_env.tcl**: Used a means to inject arbitrary TCL into the start of the build flow. Controls synthesis and implementation strategies, and sets the host_clock frequency before the clock generator (MCMM) is synthesized. * **<BASE>.env.tcl**: Used a means to inject arbitrary TCL into the start of the build flow. Controls synthesis and implementation strategies, and sets the host_clock frequency before the clock generator (MCMM) is synthesized.
* **<BASE>_ila_insert_vivado.tcl**: Synthesizes an ILA for the design. See :ref:`auto-ila` for more details about using ILAs in FireSim. * **<BASE>.ila_insert_vivado.tcl**: Synthesizes an ILA for the design. See :ref:`auto-ila` for more details about using ILAs in FireSim.
* **<BASE>_ila_insert_{inst, ports, wires}.v**: Instantiated in the FPGA project via ```include`` directives to instantiate the generated ILA. * **<BASE>.ila_insert_{inst, ports, wires}.v**: Instantiated in the FPGA project via ```include`` directives to instantiate the generated ILA.
Meta-simulation Files Meta-simulation Files
------------------------------------- -------------------------------------
These are additional sources used only in MIDAS-level simulators These are additional sources used only in MIDAS-level simulators
* **<BASE>_const.vh**: Verilog macros to define variable width fields. * **<BASE>.const.vh**: Verilog macros to define variable width fields.