From d1bddb4ea75a9df6933d8281f9d66cb9cce5df0c Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 1 Jul 2023 20:12:25 -0700 Subject: [PATCH 1/6] u200 support test --- .../xilinx_alveo_u200.yaml | 16 + deploy/buildtools/bitbuilder.py | 5 + deploy/firesim | 3 +- deploy/runtools/run_farm_deploy_managers.py | 5 + platforms/xilinx_alveo_u200/.gitignore | 5 + .../xilinx_alveo_u200/build-bitstream.sh | 1 + .../cl_firesim/design/axi_tieoff_master.v | 1 + .../cl_firesim/design/bitstream_config.xdc | 1 + .../cl_firesim/design/firesim_wrapper.v | 1 + .../cl_firesim/scripts/au200.tcl | 23 ++ .../cl_firesim/scripts/create_bd_2021.1.tcl | 384 +++++++++++++++++ .../cl_firesim/scripts/create_bd_2022.2.tcl | 389 ++++++++++++++++++ .../scripts/implementation_2021.1.tcl | 1 + .../scripts/implementation_2022.2.tcl | 1 + .../cl_firesim/scripts/main.tcl | 1 + .../cl_firesim/scripts/platform_env.tcl | 1 + .../cl_firesim/scripts/synthesis.tcl | 1 + platforms/xilinx_alveo_u200/scripts | 1 + .../xilinx_alveo_u250/build-bitstream.sh | 2 +- sim/make/driver.mk | 19 + sim/make/fpga.mk | 2 + .../src/main/cc/simif_xilinx_alveo_u200.cc | 1 + 22 files changed, 862 insertions(+), 2 deletions(-) create mode 100644 deploy/bit-builder-recipes/xilinx_alveo_u200.yaml create mode 100644 platforms/xilinx_alveo_u200/.gitignore create mode 120000 platforms/xilinx_alveo_u200/build-bitstream.sh create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/design/axi_tieoff_master.v create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/design/bitstream_config.xdc create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/design/firesim_wrapper.v create mode 100644 platforms/xilinx_alveo_u200/cl_firesim/scripts/au200.tcl create mode 100644 platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl create mode 100644 platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2021.1.tcl create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.2.tcl create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/scripts/main.tcl create mode 100644 platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl create mode 120000 platforms/xilinx_alveo_u200/cl_firesim/scripts/synthesis.tcl create mode 120000 platforms/xilinx_alveo_u200/scripts create mode 120000 sim/midas/src/main/cc/simif_xilinx_alveo_u200.cc diff --git a/deploy/bit-builder-recipes/xilinx_alveo_u200.yaml b/deploy/bit-builder-recipes/xilinx_alveo_u200.yaml new file mode 100644 index 00000000..2ed258a8 --- /dev/null +++ b/deploy/bit-builder-recipes/xilinx_alveo_u200.yaml @@ -0,0 +1,16 @@ +# Build-time bitbuilder design configuration for the FireSim Simulation Manager +# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params. + +########### +# Schema: +########### +# # Class name of the bitbuilder type. +# # This can be determined from `deploy/buildtools/bitbuilder.py`). +# bitbuilder_type: +# args: +# # Bitbuilder arguments that are passed to the `BitBuilder` +# # object. Determined by looking at `_parse_args` function of class. +# + +bit_builder_type: XilinxAlveoU200BitBuilder +args: null diff --git a/deploy/buildtools/bitbuilder.py b/deploy/buildtools/bitbuilder.py index 44da8e83..ef58980f 100644 --- a/deploy/buildtools/bitbuilder.py +++ b/deploy/buildtools/bitbuilder.py @@ -734,6 +734,11 @@ class XilinxAlveoBitBuilder(BitBuilder): return True +class XilinxAlveoU200BitBuilder(XilinxAlveoBitBuilder): + def __init__(self, build_config: BuildConfig, args: Dict[str, Any]) -> None: + super().__init__(build_config, args) + self.BOARD_NAME = "au200" + class XilinxAlveoU280BitBuilder(XilinxAlveoBitBuilder): def __init__(self, build_config: BuildConfig, args: Dict[str, Any]) -> None: super().__init__(build_config, args) diff --git a/deploy/firesim b/deploy/firesim index 2f14aa21..7c85df36 100755 --- a/deploy/firesim +++ b/deploy/firesim @@ -184,7 +184,7 @@ def managerinit(args: argparse.Namespace): "managerinit replace start", "managerinit replace end", bf_recipe_lines) - elif args.platform == 'vitis' or args.platform == 'xilinx_alveo_u250' or args.platform == 'xilinx_alveo_u280' or args.platform == 'xilinx_vcu118' or args.platform == 'rhsresearch_nitefury_ii': + elif args.platform == 'vitis' or args.platform == 'xilinx_alveo_u250' or args.platform == 'xilinx_alveo_u280' or args.platform == 'xilinx_alveo_u200' or args.platform == 'xilinx_vcu118' or args.platform == 'rhsresearch_nitefury_ii': runfarm_default_file = "run-farm-recipes/externally_provisioned.yaml" with open(runfarm_default_file, "r") as f: rf_recipe_lines = f.readlines() @@ -193,6 +193,7 @@ def managerinit(args: argparse.Namespace): deploy_manager_map = { 'vitis': 'VitisInstanceDeployManager', + 'xilinx_alveo_u200': 'XilinxAlveoU200InstanceDeployManager', 'xilinx_alveo_u250': 'XilinxAlveoU250InstanceDeployManager', 'xilinx_alveo_u280': 'XilinxAlveoU280InstanceDeployManager', 'xilinx_vcu118': 'XilinxVCU118InstanceDeployManager', diff --git a/deploy/runtools/run_farm_deploy_managers.py b/deploy/runtools/run_farm_deploy_managers.py index dd74f3ba..0c690a1a 100644 --- a/deploy/runtools/run_farm_deploy_managers.py +++ b/deploy/runtools/run_farm_deploy_managers.py @@ -987,6 +987,11 @@ class XilinxAlveoU280InstanceDeployManager(XilinxAlveoInstanceDeployManager): super().__init__(parent_node) self.PLATFORM_NAME = "xilinx_alveo_u280" +class XilinxAlveoU200InstanceDeployManager(XilinxAlveoInstanceDeployManager): + def __init__(self, parent_node: Inst) -> None: + super().__init__(parent_node) + self.PLATFORM_NAME = "xilinx_alveo_u200" + class RHSResearchNitefuryIIInstanceDeployManager(XilinxAlveoInstanceDeployManager): def __init__(self, parent_node: Inst) -> None: super().__init__(parent_node) diff --git a/platforms/xilinx_alveo_u200/.gitignore b/platforms/xilinx_alveo_u200/.gitignore new file mode 100644 index 00000000..f68839a2 --- /dev/null +++ b/platforms/xilinx_alveo_u200/.gitignore @@ -0,0 +1,5 @@ +.*.swp +.*.swo + +cl_* +!cl_firesim diff --git a/platforms/xilinx_alveo_u200/build-bitstream.sh b/platforms/xilinx_alveo_u200/build-bitstream.sh new file mode 120000 index 00000000..e95e4492 --- /dev/null +++ b/platforms/xilinx_alveo_u200/build-bitstream.sh @@ -0,0 +1 @@ +../xilinx_alveo_u250/build-bitstream.sh \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/design/axi_tieoff_master.v b/platforms/xilinx_alveo_u200/cl_firesim/design/axi_tieoff_master.v new file mode 120000 index 00000000..e589513a --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/design/axi_tieoff_master.v @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/design/axi_tieoff_master.v \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/design/bitstream_config.xdc b/platforms/xilinx_alveo_u200/cl_firesim/design/bitstream_config.xdc new file mode 120000 index 00000000..12883e55 --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/design/bitstream_config.xdc @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/design/bitstream_config.xdc \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/design/firesim_wrapper.v b/platforms/xilinx_alveo_u200/cl_firesim/design/firesim_wrapper.v new file mode 120000 index 00000000..f136d7b4 --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/design/firesim_wrapper.v @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/design/firesim_wrapper.v \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/au200.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/au200.tcl new file mode 100644 index 00000000..9186003a --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/au200.tcl @@ -0,0 +1,23 @@ +# ************************************************************************* +# +# Copyright 2020 Xilinx, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# ************************************************************************* + +# Adapted from https://github.com/Xilinx/open-nic-shell + +set part xcu200-fsgd2104-2-e +set board_part xilinx.com:au200:part0:1.3 +set zynq_family 0 diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl new file mode 100644 index 00000000..ab7ea16f --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl @@ -0,0 +1,384 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# The design that will be created by this Tcl script contains the following +# module references: +# axi_tieoff_master, firesim_wrapper + +# Please add the sources of those modules before sourcing this Tcl script. + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:xdma:4.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +axi_tieoff_master\ +firesim_wrapper\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell firesim_freq } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_300mhz_clk0 + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $resetn + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_clock_converter_1, and set properties + set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ] + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + # clock conversion is only available in upsizer FIFO mode. by default we are in downsizer mode so we have to manually enter the correct width. + set_property -dict [list CONFIG.MI_DATA_WIDTH.VALUE_SRC USER] $axi_dwidth_converter_0 + set_property -dict [list CONFIG.MI_DATA_WIDTH {512}] $axi_dwidth_converter_0 + set_property -dict [ list \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {16} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.ACLK_ASYNC {1} \ + ] $axi_dwidth_converter_0 + + # Create instance: axi_tieoff_master_0, and set properties + set block_name axi_tieoff_master + set block_cell_name axi_tieoff_master_0 + if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $axi_tieoff_master_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MCS_ECC {false} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + CONFIG.Debug_Signal {Disable} \ + CONFIG.RESET_BOARD_INTERFACE {resetn} \ + ] $ddr4_0 + + # Create instance: firesim_wrapper_0, and set properties + set block_name firesim_wrapper + set block_cell_name firesim_wrapper_0 + if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $firesim_wrapper_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: resetn_inv_0, and set properties + set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ] + set_property -dict [ list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $resetn_inv_0 + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [ list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.pciebar2axibar_axist_bypass {0x0000000000000000} \ + CONFIG.pf0_msix_cap_pba_bir {BAR_1} \ + CONFIG.pf0_msix_cap_table_bir {BAR_1} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {4} \ + CONFIG.xdma_wnum_chnl {4} \ + ] $xdma_0 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + set clk_wiz_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0] + set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq CONFIG.USE_LOCKED {false}] $clk_wiz_0 + + # Create interface connections + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA] + connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_out1] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_in1] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1] + connect_bd_net -net resetn_inv_0_Res [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] [get_bd_pins clk_wiz_0/reset] + connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout] + + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" $desired_host_frequency + + diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl new file mode 100644 index 00000000..cb327b54 --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl @@ -0,0 +1,389 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# The design that will be created by this Tcl script contains the following +# module references: +# axi_tieoff_master, firesim_wrapper + +# Please add the sources of those modules before sourcing this Tcl script. + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:xdma:4.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +axi_tieoff_master\ +firesim_wrapper\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell firesim_freq } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_300mhz_clk0 + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $resetn + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_clock_converter_1, and set properties + set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ] + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {16} \ + ] $axi_dwidth_converter_0 + + + # Create instance: axi_tieoff_master_0, and set properties + set block_name axi_tieoff_master + set block_cell_name axi_tieoff_master_0 + if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $axi_tieoff_master_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [list \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \ + CONFIG.USE_LOCKED {false} \ + ] $clk_wiz_0 + + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_MCS_ECC {false} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + CONFIG.Debug_Signal {Disable} \ + CONFIG.RESET_BOARD_INTERFACE {resetn} \ + ] $ddr4_0 + + + # Create instance: firesim_wrapper_0, and set properties + set block_name firesim_wrapper + set block_cell_name firesim_wrapper_0 + if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $firesim_wrapper_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: resetn_inv_0, and set properties + set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $resetn_inv_0 + + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [list \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf + + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {4} \ + CONFIG.xdma_wnum_chnl {4} \ + ] $xdma_0 + + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property CONFIG.CONST_VAL {0} $xlconstant_0 + + + # Create interface connections + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA] + connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1] + connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] + connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] + connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout] + + # Create address segments + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" $desired_host_frequency + + diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2021.1.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2021.1.tcl new file mode 120000 index 00000000..949d02bd --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2021.1.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2021.1.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.2.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.2.tcl new file mode 120000 index 00000000..5201b88e --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.2.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.2.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/main.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/main.tcl new file mode 120000 index 00000000..b0c49cbb --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/main.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/main.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl new file mode 100644 index 00000000..e8fc14de --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl @@ -0,0 +1 @@ +set jobs 12 diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/synthesis.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/synthesis.tcl new file mode 120000 index 00000000..33facbed --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/synthesis.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/synthesis.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/scripts b/platforms/xilinx_alveo_u200/scripts new file mode 120000 index 00000000..4ce79a13 --- /dev/null +++ b/platforms/xilinx_alveo_u200/scripts @@ -0,0 +1 @@ +../xilinx_alveo_u250/scripts \ No newline at end of file diff --git a/platforms/xilinx_alveo_u250/build-bitstream.sh b/platforms/xilinx_alveo_u250/build-bitstream.sh index 606e32af..46ec8f1b 100755 --- a/platforms/xilinx_alveo_u250/build-bitstream.sh +++ b/platforms/xilinx_alveo_u250/build-bitstream.sh @@ -15,7 +15,7 @@ usage() { echo " --strategy : A string to a precanned set of build directives. See aws-fpga documentation for more info/. For this platform TIMING and AREA supported." - echo " --board : FPGA board {au250,au280}." + echo " --board : FPGA board {au200,au250,au280}." echo " --help : Display this message" exit "$1" } diff --git a/sim/make/driver.mk b/sim/make/driver.mk index 2c1a9e4d..517eb40c 100644 --- a/sim/make/driver.mk +++ b/sim/make/driver.mk @@ -66,6 +66,25 @@ $(xilinx_alveo_u280): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) DRIVER="$(DRIVER_CC)" \ TOP_DIR=$(chipyard_dir) + +$(xilinx_alveo_u200): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \ + -idirafter ${CONDA_PREFIX}/include -idirafter /usr/include +$(xilinx_alveo_u200): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \ + -L${CONDA_PREFIX}/lib -Wl,-rpath-link=/usr/lib/x86_64-linux-gnu -L/usr/lib/x86_64-linux-gnu + +# Compile Driver +$(xilinx_alveo_u200): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h) + mkdir -p $(OUTPUT_DIR)/build + cp $(header) $(OUTPUT_DIR)/build/ + $(MAKE) -C $(simif_dir) driver MAIN=$(PLATFORM) PLATFORM=$(PLATFORM) \ + DRIVER_NAME=$(DESIGN) \ + GEN_FILE_BASENAME=$(BASE_FILE_NAME) \ + GEN_DIR=$(OUTPUT_DIR)/build \ + OUT_DIR=$(OUTPUT_DIR) \ + DRIVER="$(DRIVER_CC)" \ + TOP_DIR=$(chipyard_dir) + + $(xilinx_vcu118): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \ -idirafter ${CONDA_PREFIX}/include -idirafter /usr/include $(xilinx_vcu118): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \ diff --git a/sim/make/fpga.mk b/sim/make/fpga.mk index 8a1170d5..663f817f 100644 --- a/sim/make/fpga.mk +++ b/sim/make/fpga.mk @@ -12,6 +12,8 @@ else ifeq ($(PLATFORM), xilinx_alveo_u250) board_dir := $(platforms_dir)/xilinx_alveo_u250 else ifeq ($(PLATFORM), xilinx_alveo_u280) board_dir := $(platforms_dir)/xilinx_alveo_u280 +else ifeq ($(PLATFORM), xilinx_alveo_u200) +board_dir := $(platforms_dir)/xilinx_alveo_u200 else ifeq ($(PLATFORM), xilinx_vcu118) board_dir := $(platforms_dir)/xilinx_vcu118/garnet-firesim else ifeq ($(PLATFORM), rhsresearch_nitefury_ii) diff --git a/sim/midas/src/main/cc/simif_xilinx_alveo_u200.cc b/sim/midas/src/main/cc/simif_xilinx_alveo_u200.cc new file mode 120000 index 00000000..ed518a38 --- /dev/null +++ b/sim/midas/src/main/cc/simif_xilinx_alveo_u200.cc @@ -0,0 +1 @@ +simif_xilinx_alveo_u250.cc \ No newline at end of file From 302ce66d6498ed36a64dbb8818afdda875f89ec7 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 1 Jul 2023 20:16:06 -0700 Subject: [PATCH 2/6] more stuff --- .github/scripts/run-local-buildbitstreams.py | 2 +- .../sample_config_build_recipes.yaml | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/.github/scripts/run-local-buildbitstreams.py b/.github/scripts/run-local-buildbitstreams.py index dae8d1cc..75ed3eab 100755 --- a/.github/scripts/run-local-buildbitstreams.py +++ b/.github/scripts/run-local-buildbitstreams.py @@ -241,7 +241,7 @@ def run_local_buildbitstreams(): batch_hwdbs_in = [ ("nitefury_firesim_rocket_singlecore_no_nic", "rhsresearch_nitefury_ii", "vitis:2022.1"), ("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"), - ("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vivado:2021.1"), + ("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vivado:2021.1"), ("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2019.1"), ] diff --git a/deploy/sample-backup-configs/sample_config_build_recipes.yaml b/deploy/sample-backup-configs/sample_config_build_recipes.yaml index f026919a..dc4e6672 100644 --- a/deploy/sample-backup-configs/sample_config_build_recipes.yaml +++ b/deploy/sample-backup-configs/sample_config_build_recipes.yaml @@ -317,6 +317,21 @@ alveo_u280_firesim_rocket_singlecore_no_nic: metasim_customruntimeconfig: null bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u280.yaml +# Additional Xilinx Alveo U200-only Config +alveo_u200_firesim_rocket_singlecore_no_nic: + PLATFORM: xilinx_alveo_u200 + TARGET_PROJECT: firesim + DESIGN: FireSim + TARGET_CONFIG: FireSimRocketConfig + PLATFORM_CONFIG: BaseXilinxAlveoConfig + deploy_quintuplet: null + platform_config_args: + fpga_frequency: 15 + build_strategy: TIMING + post_build_hook: null + metasim_customruntimeconfig: null + bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u200.yaml + # Xilinx VCU118-only Config xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic: PLATFORM: xilinx_vcu118 From bd2ae0a978a9e129c01f2b850af864d9c7c5bb11 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 1 Jul 2023 20:34:28 -0700 Subject: [PATCH 3/6] u200 build --- deploy/sample-backup-configs/sample_config_build.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/deploy/sample-backup-configs/sample_config_build.yaml b/deploy/sample-backup-configs/sample_config_build.yaml index 74059e55..7dc5ace7 100644 --- a/deploy/sample-backup-configs/sample_config_build.yaml +++ b/deploy/sample-backup-configs/sample_config_build.yaml @@ -48,6 +48,7 @@ builds_to_run: # Configs for Xilinx Alveo U250/U280 # - alveo_u250_firesim_rocket_singlecore_no_nic + # - alveo_u200_firesim_rocket_singlecore_no_nic # - alveo_u280_firesim_rocket_singlecore_no_nic # Config for Xilinx VCU118 From 3d758a87322d5fdafac4af04101b985846768a12 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sun, 2 Jul 2023 19:26:03 -0700 Subject: [PATCH 4/6] various fixes --- deploy/sample-backup-configs/sample_config_hwdb.yaml | 4 ++++ docs/Advanced-Usage/Manager/HELP_OUTPUT | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/deploy/sample-backup-configs/sample_config_hwdb.yaml b/deploy/sample-backup-configs/sample_config_hwdb.yaml index 3958a601..c4d79bc1 100644 --- a/deploy/sample-backup-configs/sample_config_hwdb.yaml +++ b/deploy/sample-backup-configs/sample_config_hwdb.yaml @@ -68,6 +68,10 @@ alveo_u250_firesim_rocket_singlecore_no_nic: bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/c41e43a1b30b88434330476195481da0d58695a8/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null +alveo_u200_firesim_rocket_singlecore_no_nic: + bitstream_tar: REPLACE_THIS + deploy_quintuplet_override: null + custom_runtime_config: null alveo_u280_firesim_rocket_singlecore_no_nic: bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/58912148918d390210661c1cfa6ae7e774199f6a/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null diff --git a/docs/Advanced-Usage/Manager/HELP_OUTPUT b/docs/Advanced-Usage/Manager/HELP_OUTPUT index a3216a2b..4adab0e6 100644 --- a/docs/Advanced-Usage/Manager/HELP_OUTPUT +++ b/docs/Advanced-Usage/Manager/HELP_OUTPUT @@ -4,7 +4,7 @@ usage: firesim [-h] [-c RUNTIMECONFIGFILE] [-b BUILDCONFIGFILE] [-g TERMINATESOMEF12] [-i TERMINATESOMEF14] [-m TERMINATESOMEM416] [--terminatesome TERMINATESOME] [-q] [-t LAUNCHTIME] - [--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}] + [--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u200,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}] {managerinit,infrasetup,boot,kill,runworkload,buildbitstream,builddriver,enumeratefpgas,tar2afi,runcheck,launchrunfarm,terminaterunfarm,shareagfi} FireSim Simulation Manager. @@ -76,6 +76,6 @@ options: Give the "Y-m-d--H-M-S" prefix of results-build directory. Useful for tar2afi when finishing a partial buildbitstream - --platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118} + --platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u200,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118} Required argument for "managerinit" to specify which platform you will be using From d5e4b39a269623b6278a3d08d3e3a0532b983b9a Mon Sep 17 00:00:00 2001 From: sagark Date: Sun, 2 Jul 2023 22:43:18 -0700 Subject: [PATCH 5/6] Update local bitstream(s) [ci skip] --- deploy/sample-backup-configs/sample_config_hwdb.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/deploy/sample-backup-configs/sample_config_hwdb.yaml b/deploy/sample-backup-configs/sample_config_hwdb.yaml index c4d79bc1..0b468084 100644 --- a/deploy/sample-backup-configs/sample_config_hwdb.yaml +++ b/deploy/sample-backup-configs/sample_config_hwdb.yaml @@ -65,11 +65,11 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic: custom_runtime_config: null # DOCREF START: Xilinx Alveo HWDB Entries alveo_u250_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/c41e43a1b30b88434330476195481da0d58695a8/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/ed04a2e3f5dc6b14ef0acfbb1b8ae4963bdacd3e/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null alveo_u200_firesim_rocket_singlecore_no_nic: - bitstream_tar: REPLACE_THIS + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/15490e0486604006b9f2f6a4188a7ec57ed06276/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null alveo_u280_firesim_rocket_singlecore_no_nic: @@ -78,11 +78,15 @@ alveo_u280_firesim_rocket_singlecore_no_nic: custom_runtime_config: null # DOCREF END: Xilinx Alveo HWDB Entries xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/b448a21ee269d116515b893d4e945edb5c349928/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0d8b46c43c3fa596955d9bb674833c2c7b8f9b09/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null nitefury_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/2db0f64a7670cdc2c7d528e2170cd1bf111208c6/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/69531b76799f73a049ab2d9856b2ba00151872af/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null + + + + From 2fce85ca0e3af42aac0f8eff159b7f729c55c44b Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Mon, 3 Jul 2023 13:20:28 -0700 Subject: [PATCH 6/6] revert ci changes --- .github/scripts/run-local-buildbitstreams.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/run-local-buildbitstreams.py b/.github/scripts/run-local-buildbitstreams.py index 75ed3eab..dae8d1cc 100755 --- a/.github/scripts/run-local-buildbitstreams.py +++ b/.github/scripts/run-local-buildbitstreams.py @@ -241,7 +241,7 @@ def run_local_buildbitstreams(): batch_hwdbs_in = [ ("nitefury_firesim_rocket_singlecore_no_nic", "rhsresearch_nitefury_ii", "vitis:2022.1"), ("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"), - ("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vivado:2021.1"), + ("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vivado:2021.1"), ("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2019.1"), ]