Merge pull request #1581 from firesim/u200-test
Add support for Alveo U200
This commit is contained in:
Sagar Karandikar
GitHub
commit
955afacc6d
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@ -0,0 +1,16 @@
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# Build-time bitbuilder design configuration for the FireSim Simulation Manager
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# See https://docs.fires.im/en/stable/Advanced-Usage/Manager/Manager-Configuration-Files.html for documentation of all of these params.
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###########
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# Schema:
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###########
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# # Class name of the bitbuilder type.
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# # This can be determined from `deploy/buildtools/bitbuilder.py`).
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# bitbuilder_type: <TYPE NAME>
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# args:
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# # Bitbuilder arguments that are passed to the `BitBuilder`
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# # object. Determined by looking at `_parse_args` function of class.
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# <K/V pairs of args>
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bit_builder_type: XilinxAlveoU200BitBuilder
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args: null
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@ -734,6 +734,11 @@ class XilinxAlveoBitBuilder(BitBuilder):
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return True
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class XilinxAlveoU200BitBuilder(XilinxAlveoBitBuilder):
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def __init__(self, build_config: BuildConfig, args: Dict[str, Any]) -> None:
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super().__init__(build_config, args)
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self.BOARD_NAME = "au200"
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class XilinxAlveoU280BitBuilder(XilinxAlveoBitBuilder):
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def __init__(self, build_config: BuildConfig, args: Dict[str, Any]) -> None:
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super().__init__(build_config, args)
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@ -184,7 +184,7 @@ def managerinit(args: argparse.Namespace):
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"managerinit replace start",
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"managerinit replace end",
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bf_recipe_lines)
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elif args.platform == 'vitis' or args.platform == 'xilinx_alveo_u250' or args.platform == 'xilinx_alveo_u280' or args.platform == 'xilinx_vcu118' or args.platform == 'rhsresearch_nitefury_ii':
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elif args.platform == 'vitis' or args.platform == 'xilinx_alveo_u250' or args.platform == 'xilinx_alveo_u280' or args.platform == 'xilinx_alveo_u200' or args.platform == 'xilinx_vcu118' or args.platform == 'rhsresearch_nitefury_ii':
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runfarm_default_file = "run-farm-recipes/externally_provisioned.yaml"
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with open(runfarm_default_file, "r") as f:
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rf_recipe_lines = f.readlines()
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@ -193,6 +193,7 @@ def managerinit(args: argparse.Namespace):
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deploy_manager_map = {
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'vitis': 'VitisInstanceDeployManager',
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'xilinx_alveo_u200': 'XilinxAlveoU200InstanceDeployManager',
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'xilinx_alveo_u250': 'XilinxAlveoU250InstanceDeployManager',
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'xilinx_alveo_u280': 'XilinxAlveoU280InstanceDeployManager',
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'xilinx_vcu118': 'XilinxVCU118InstanceDeployManager',
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@ -987,6 +987,11 @@ class XilinxAlveoU280InstanceDeployManager(XilinxAlveoInstanceDeployManager):
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super().__init__(parent_node)
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self.PLATFORM_NAME = "xilinx_alveo_u280"
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class XilinxAlveoU200InstanceDeployManager(XilinxAlveoInstanceDeployManager):
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def __init__(self, parent_node: Inst) -> None:
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super().__init__(parent_node)
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self.PLATFORM_NAME = "xilinx_alveo_u200"
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class RHSResearchNitefuryIIInstanceDeployManager(XilinxAlveoInstanceDeployManager):
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def __init__(self, parent_node: Inst) -> None:
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super().__init__(parent_node)
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@ -48,6 +48,7 @@ builds_to_run:
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# Configs for Xilinx Alveo U250/U280
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# - alveo_u250_firesim_rocket_singlecore_no_nic
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# - alveo_u200_firesim_rocket_singlecore_no_nic
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# - alveo_u280_firesim_rocket_singlecore_no_nic
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# Config for Xilinx VCU118
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@ -317,6 +317,21 @@ alveo_u280_firesim_rocket_singlecore_no_nic:
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metasim_customruntimeconfig: null
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bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u280.yaml
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# Additional Xilinx Alveo U200-only Config
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alveo_u200_firesim_rocket_singlecore_no_nic:
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PLATFORM: xilinx_alveo_u200
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TARGET_PROJECT: firesim
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DESIGN: FireSim
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TARGET_CONFIG: FireSimRocketConfig
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PLATFORM_CONFIG: BaseXilinxAlveoConfig
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deploy_quintuplet: null
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platform_config_args:
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fpga_frequency: 15
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build_strategy: TIMING
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post_build_hook: null
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metasim_customruntimeconfig: null
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bit_builder_recipe: bit-builder-recipes/xilinx_alveo_u200.yaml
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# Xilinx VCU118-only Config
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xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic:
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PLATFORM: xilinx_vcu118
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@ -65,7 +65,11 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic:
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custom_runtime_config: null
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# DOCREF START: Xilinx Alveo HWDB Entries
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alveo_u250_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/c41e43a1b30b88434330476195481da0d58695a8/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/ed04a2e3f5dc6b14ef0acfbb1b8ae4963bdacd3e/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u200_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/15490e0486604006b9f2f6a4188a7ec57ed06276/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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alveo_u280_firesim_rocket_singlecore_no_nic:
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@ -74,11 +78,15 @@ alveo_u280_firesim_rocket_singlecore_no_nic:
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custom_runtime_config: null
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# DOCREF END: Xilinx Alveo HWDB Entries
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xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/b448a21ee269d116515b893d4e945edb5c349928/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0d8b46c43c3fa596955d9bb674833c2c7b8f9b09/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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nitefury_firesim_rocket_singlecore_no_nic:
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/2db0f64a7670cdc2c7d528e2170cd1bf111208c6/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
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bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/69531b76799f73a049ab2d9856b2ba00151872af/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
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deploy_quintuplet_override: null
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custom_runtime_config: null
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@ -4,7 +4,7 @@ usage: firesim [-h] [-c RUNTIMECONFIGFILE] [-b BUILDCONFIGFILE]
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[-g TERMINATESOMEF12] [-i TERMINATESOMEF14]
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[-m TERMINATESOMEM416] [--terminatesome TERMINATESOME] [-q]
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[-t LAUNCHTIME]
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[--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}]
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[--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u200,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}]
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{managerinit,infrasetup,boot,kill,runworkload,buildbitstream,builddriver,enumeratefpgas,tar2afi,runcheck,launchrunfarm,terminaterunfarm,shareagfi}
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FireSim Simulation Manager.
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@ -76,6 +76,6 @@ options:
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Give the "Y-m-d--H-M-S" prefix of results-build
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directory. Useful for tar2afi when finishing a partial
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buildbitstream
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--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}
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--platform {f1,rhsresearch_nitefury_ii,vitis,xilinx_alveo_u200,xilinx_alveo_u250,xilinx_alveo_u280,xilinx_vcu118}
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Required argument for "managerinit" to specify which
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platform you will be using
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@ -0,0 +1,5 @@
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.*.swp
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.*.swo
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cl_*
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!cl_firesim
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@ -0,0 +1 @@
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../xilinx_alveo_u250/build-bitstream.sh
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@ -0,0 +1 @@
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../../../xilinx_alveo_u250/cl_firesim/design/axi_tieoff_master.v
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@ -0,0 +1 @@
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../../../xilinx_alveo_u250/cl_firesim/design/bitstream_config.xdc
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@ -0,0 +1 @@
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../../../xilinx_alveo_u250/cl_firesim/design/firesim_wrapper.v
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@ -0,0 +1,23 @@
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# *************************************************************************
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#
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# Copyright 2020 Xilinx, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# *************************************************************************
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# Adapted from https://github.com/Xilinx/open-nic-shell
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set part xcu200-fsgd2104-2-e
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set board_part xilinx.com:au200:part0:1.3
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set zynq_family 0
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@ -0,0 +1,384 @@
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################################################################
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# This is a generated script based on design: design_1
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# The design that will be created by this Tcl script contains the following
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# module references:
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# axi_tieoff_master, firesim_wrapper
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# Please add the sources of those modules before sourcing this Tcl script.
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name design_1
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
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|
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create_bd_design $design_name
|
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|
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
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current_bd_design $design_name
|
||||
|
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}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
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if { $nRet != 0 } {
|
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_clock_converter:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:ddr4:2.2\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_tieoff_master\
|
||||
firesim_wrapper\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell firesim_freq } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ]
|
||||
|
||||
set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {300000000} \
|
||||
] $default_300mhz_clk0
|
||||
|
||||
set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ]
|
||||
|
||||
set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $pcie_refclk
|
||||
|
||||
|
||||
# Create ports
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $pcie_perstn
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
|
||||
# Create instance: axi_clock_converter_0, and set properties
|
||||
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
||||
|
||||
# Create instance: axi_clock_converter_1, and set properties
|
||||
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
|
||||
|
||||
# Create instance: axi_dwidth_converter_0, and set properties
|
||||
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
|
||||
# clock conversion is only available in upsizer FIFO mode. by default we are in downsizer mode so we have to manually enter the correct width.
|
||||
set_property -dict [list CONFIG.MI_DATA_WIDTH.VALUE_SRC USER] $axi_dwidth_converter_0
|
||||
set_property -dict [list CONFIG.MI_DATA_WIDTH {512}] $axi_dwidth_converter_0
|
||||
set_property -dict [ list \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SI_ID_WIDTH {16} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
] $axi_dwidth_converter_0
|
||||
|
||||
# Create instance: axi_tieoff_master_0, and set properties
|
||||
set block_name axi_tieoff_master
|
||||
set block_cell_name axi_tieoff_master_0
|
||||
if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_tieoff_master_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: ddr4_0, and set properties
|
||||
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {resetn} \
|
||||
] $ddr4_0
|
||||
|
||||
# Create instance: firesim_wrapper_0, and set properties
|
||||
set block_name firesim_wrapper
|
||||
set block_cell_name firesim_wrapper_0
|
||||
if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $firesim_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create instance: proc_sys_reset_1, and set properties
|
||||
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
|
||||
|
||||
# Create instance: resetn_inv_0, and set properties
|
||||
set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $resetn_inv_0
|
||||
|
||||
# Create instance: util_ds_buf, and set properties
|
||||
set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {IBUFDSGTE} \
|
||||
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $util_ds_buf
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \
|
||||
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {32} \
|
||||
CONFIG.pciebar2axibar_axist_bypass {0x0000000000000000} \
|
||||
CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
|
||||
CONFIG.pf0_msix_cap_table_bir {BAR_1} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
|
||||
CONFIG.xdma_rnum_chnl {4} \
|
||||
CONFIG.xdma_wnum_chnl {4} \
|
||||
] $xdma_0
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CONST_VAL {0} \
|
||||
] $xlconstant_0
|
||||
|
||||
set clk_wiz_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0]
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq CONFIG.USE_LOCKED {false}] $clk_wiz_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4]
|
||||
connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
|
||||
connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0]
|
||||
connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_out1]
|
||||
connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_in1]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1]
|
||||
connect_bd_net -net resetn_inv_0_Res [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] [get_bd_pins clk_wiz_0/reset]
|
||||
connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||
connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout]
|
||||
|
||||
|
||||
# Create address segments
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design "" $desired_host_frequency
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
|
||||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2022.2
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# axi_tieoff_master, firesim_wrapper
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_clock_converter:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:ddr4:2.2\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_tieoff_master\
|
||||
firesim_wrapper\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell firesim_freq } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ]
|
||||
|
||||
set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {300000000} \
|
||||
] $default_300mhz_clk0
|
||||
|
||||
set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ]
|
||||
|
||||
set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $pcie_refclk
|
||||
|
||||
|
||||
# Create ports
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $pcie_perstn
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
|
||||
# Create instance: axi_clock_converter_0, and set properties
|
||||
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
||||
|
||||
# Create instance: axi_clock_converter_1, and set properties
|
||||
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
|
||||
|
||||
# Create instance: axi_dwidth_converter_0, and set properties
|
||||
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {512} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SI_ID_WIDTH {16} \
|
||||
] $axi_dwidth_converter_0
|
||||
|
||||
|
||||
# Create instance: axi_tieoff_master_0, and set properties
|
||||
set block_name axi_tieoff_master
|
||||
set block_cell_name axi_tieoff_master_0
|
||||
if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_tieoff_master_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: clk_wiz_0, and set properties
|
||||
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \
|
||||
CONFIG.USE_LOCKED {false} \
|
||||
] $clk_wiz_0
|
||||
|
||||
|
||||
# Create instance: ddr4_0, and set properties
|
||||
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {34} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {true} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {resetn} \
|
||||
] $ddr4_0
|
||||
|
||||
|
||||
# Create instance: firesim_wrapper_0, and set properties
|
||||
set block_name firesim_wrapper
|
||||
set block_cell_name firesim_wrapper_0
|
||||
if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $firesim_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create instance: proc_sys_reset_1, and set properties
|
||||
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
|
||||
|
||||
# Create instance: resetn_inv_0, and set properties
|
||||
set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $resetn_inv_0
|
||||
|
||||
|
||||
# Create instance: util_ds_buf, and set properties
|
||||
set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $util_ds_buf
|
||||
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \
|
||||
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {32} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
|
||||
CONFIG.xdma_rnum_chnl {4} \
|
||||
CONFIG.xdma_wnum_chnl {4} \
|
||||
] $xdma_0
|
||||
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property CONFIG.CONST_VAL {0} $xlconstant_0
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4]
|
||||
connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
|
||||
connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0]
|
||||
connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1]
|
||||
connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res]
|
||||
connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||
connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout]
|
||||
|
||||
# Create address segments
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design "" $desired_host_frequency
|
||||
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2021.1.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.2.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/main.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
set jobs 12
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/synthesis.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
../xilinx_alveo_u250/scripts
|
||||
|
|
@ -15,7 +15,7 @@ usage() {
|
|||
echo " --strategy : A string to a precanned set of build directives.
|
||||
See aws-fpga documentation for more info/.
|
||||
For this platform TIMING and AREA supported."
|
||||
echo " --board : FPGA board {au250,au280}."
|
||||
echo " --board : FPGA board {au200,au250,au280}."
|
||||
echo " --help : Display this message"
|
||||
exit "$1"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -66,6 +66,25 @@ $(xilinx_alveo_u280): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
|||
DRIVER="$(DRIVER_CC)" \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
|
||||
$(xilinx_alveo_u200): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
|
||||
-idirafter ${CONDA_PREFIX}/include -idirafter /usr/include
|
||||
$(xilinx_alveo_u200): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \
|
||||
-L${CONDA_PREFIX}/lib -Wl,-rpath-link=/usr/lib/x86_64-linux-gnu -L/usr/lib/x86_64-linux-gnu
|
||||
|
||||
# Compile Driver
|
||||
$(xilinx_alveo_u200): $(header) $(DRIVER_CC) $(DRIVER_H) $(midas_cc) $(midas_h)
|
||||
mkdir -p $(OUTPUT_DIR)/build
|
||||
cp $(header) $(OUTPUT_DIR)/build/
|
||||
$(MAKE) -C $(simif_dir) driver MAIN=$(PLATFORM) PLATFORM=$(PLATFORM) \
|
||||
DRIVER_NAME=$(DESIGN) \
|
||||
GEN_FILE_BASENAME=$(BASE_FILE_NAME) \
|
||||
GEN_DIR=$(OUTPUT_DIR)/build \
|
||||
OUT_DIR=$(OUTPUT_DIR) \
|
||||
DRIVER="$(DRIVER_CC)" \
|
||||
TOP_DIR=$(chipyard_dir)
|
||||
|
||||
|
||||
$(xilinx_vcu118): export CXXFLAGS := $(CXXFLAGS) $(common_cxx_flags) $(DRIVER_CXXOPTS) \
|
||||
-idirafter ${CONDA_PREFIX}/include -idirafter /usr/include
|
||||
$(xilinx_vcu118): export LDFLAGS := $(LDFLAGS) $(common_ld_flags) -Wl,-rpath='$$$$ORIGIN' \
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@ else ifeq ($(PLATFORM), xilinx_alveo_u250)
|
|||
board_dir := $(platforms_dir)/xilinx_alveo_u250
|
||||
else ifeq ($(PLATFORM), xilinx_alveo_u280)
|
||||
board_dir := $(platforms_dir)/xilinx_alveo_u280
|
||||
else ifeq ($(PLATFORM), xilinx_alveo_u200)
|
||||
board_dir := $(platforms_dir)/xilinx_alveo_u200
|
||||
else ifeq ($(PLATFORM), xilinx_vcu118)
|
||||
board_dir := $(platforms_dir)/xilinx_vcu118/garnet-firesim
|
||||
else ifeq ($(PLATFORM), rhsresearch_nitefury_ii)
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
simif_xilinx_alveo_u250.cc
|
||||
Loading…
Reference in New Issue