tweak titles

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/Assertion-Synthesis.rst

@@ -1,5 +1,5 @@
-Assertion Synthesis: Catching Assertions when Running on the FPGA
-===================================================================
+Assertion Synthesis: Catching RTL Assertions on the FPGA
+========================================================================
 
 Golden Gate can synthesize assertions present in FIRRTL (implemented as ``stop``
 statements) that would otherwise be lost in the FPGA synthesis flow. Rocket

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/Debugging-Hardware-Using-ILA.rst

@@ -1,5 +1,5 @@
-Debugging Using FPGA Integrated Logic Analyzers (ILA)
-=====================================================
+AutoILA: Simple Integrated Logic Analyzer (ILA) Insertion
+===================================================================
 
 Sometimes it takes too long to simulate FireSim on RTL simulators, and
 in some occasions we would also like to debug the simulation infrastructure

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/Printf-Synthesis.rst

@@ -1,4 +1,4 @@
-Printf Synthesis: Capturing printf Calls in RTL when Running on the FPGA
+Printf Synthesis: Capturing RTL printf Calls when Running on the FPGA
 =============================================================================
 
 Golden Gate can synthesize printfs present in FIRRTL (implemented as ``printf``

docs/Advanced-Usage/Debugging-and-Profiling-on-FPGA/TracerV-with-FlameGraph.rst

@@ -1,4 +1,7 @@
-Profiling with TracerV + FlameGraphs
-=====================================
+TracerV+Flame Graphs: Profiling Software with Out-of-Band Flame Graph Generation
+=================================================================================
+
+TODO
+