Add initial program_fpga.py script
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abejgonzalez
parent
b99c0bfcc0
commit
8104cd3f66
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#!/usr/bin/env python3
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import argparse
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import os
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import subprocess
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import sys
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import pwd
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import re
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from pathlib import Path
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from typing import Optional, Dict, Any, List
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pciDevicesPath = Path('/sys/bus/pci/devices')
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def get_bridge_bdf(id: str) -> str:
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for entry in pciDevicesPath.iterdir():
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if re.match('^0000:' + re.escape(id) + ':[a-fA-F0-9]{2}\.[0-7]$', entry.name):
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bridgePath = entry.resolve().absolute().parent
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if bridgePath.exists():
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return bridgePath.name
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print(":ERROR: Unable to obtain bridge BDF")
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sys.exit(1)
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def get_fpga_bdfs(id: str) -> List[str]:
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result = []
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for entry in pciDevicesPath.iterdir():
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if re.match('^0000:' + re.escape(id) + ':[a-fA-F0-9]{2}\.[0-7]$', entry.name):
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result.append(entry.name)
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return result
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def get_fpga_devs(id) -> List[Path]:
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def readUevent(path: Path) -> Dict[Any, Any]:
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if not (path / 'uevent').exists():
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return {}
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return { entry[0]: entry[1] for entry in [line.strip('\n\r ').split('=') for line in open(f'{path}/uevent', 'r').readlines()] if len(entry) >= 2 }
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def xdmaResolver(path: Path) -> List[Path]:
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xdmaDevs = []
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for f in ['resource', 'resource0', 'resource1']:
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rsrcPath = (path / f)
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if rsrcPath.exists():
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xdmaDevs.append(rsrcPath)
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xdmaPath = (path / 'xdma')
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if xdmaPath.is_dir():
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ueventEntries = [readUevent(xdmaPath / entry.name) for entry in xdmaPath.iterdir() if (xdmaPath / entry.name).is_dir()]
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xdmaDevs.extend([Path('/dev') / uevent['DEVNAME'] for uevent in ueventEntries if 'DEVNAME' in uevent and (Path('/dev') / uevent['DEVNAME']).exists()])
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return xdmaDevs
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resolvers = {
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'xdma' : xdmaResolver
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}
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returnDevs = []
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fpgaDevices = get_fpga_bdfs(id)
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for fpgaDev in fpgaDevices:
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path = pciDevicesPath / fpgaDev
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fpgaDevUevent = readUevent(path)
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if 'DRIVER' not in fpgaDevUevent:
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print(":WARNING: Verify that 'xdma' driver is loaded")
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continue
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if fpgaDevUevent['DRIVER'] not in resolvers:
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continue
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returnDevs.extend(resolvers[fpgaDevUevent['DRIVER']](path.resolve()))
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return returnDevs
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# clear SERR bit in command register
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# https://support.xilinx.com/s/question/0D52E00006hpjPHSAY/dell-r720-poweredge-server-reboots-on-fpga-reprogramming?language=en_US
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def clear_serr(id: str) -> None:
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bridgeBDF = get_bridge_bdf(id)
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run = subprocess.run(['setpci', '-s', bridgeBDF, 'COMMAND=0000:0100'])
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if run.returncode != 0:
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print(":ERROR: Unable to clear SERR bit")
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sys.exit(1)
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# clear fatal error reporting enable bit in the device control register
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# https://support.xilinx.com/s/question/0D52E00006hpjPHSAY/dell-r720-poweredge-server-reboots-on-fpga-reprogramming?language=en_US
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def clear_fatal_error_reporting(id: str) -> None:
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bridgeBDF = get_bridge_bdf(id)
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run = subprocess.run(['setpci', '-s', bridgeBDF, 'CAP_EXP+8.w=0000:0004'])
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if run.returncode != 0:
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print(":ERROR: Unable to clear SERR bit")
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sys.exit(1)
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def write_to_linux_device_path(path: Path, data: str = '1\n') -> None:
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try:
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open(path, 'w').write(data)
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except:
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print(f":ERROR: Cannot write to {path} value: {data}")
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sys.exit(1)
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def remove(id: str) -> None:
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bridgeBDF = get_bridge_bdf(id)
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deviceBDFs = get_fpga_bdfs(id)
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for deviceBDF in deviceBDFs:
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removePath = pciDevicesPath / bridgeBDF / deviceBDF / 'remove'
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if removePath.exists():
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write_to_linux_device_path(removePath)
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def rescan(id: str) -> None:
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bridgeBDF = get_bridge_bdf(id)
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if bridgeBDF is not None:
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rescanPath = pciDevicesPath / bridgeBDF / 'rescan'
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write_to_linux_device_path(rescanPath)
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else:
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write_to_linux_device_path('/sys/bus/pci/rescan')
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# enable memory mapped transfers for the fpga
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# https://support.xilinx.com/s/question/0D52E00006iHlNoSAK/lspci-reports-bar-0-disabled?language=en_US
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def enable_memmapped_transfers(id: str) -> None:
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deviceBDFs = get_fpga_bdfs(id)
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for deviceBDF in deviceBDFs:
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run = subprocess.run(['setpci', '-s', deviceBDF, 'COMMAND=0x02'])
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if run.returncode != 0:
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print(f":ERROR: Unable to enable memmapped transfers on {deviceBDF}")
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sys.exit(1)
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def program_fpga(serial: str, board: str, bitstream: str) -> None:
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print(":WARNING: This only can target the 1st FPGA on a machine currently...")
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pVivado = subprocess.Popen(
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[
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'vivado',
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'-mode', 'tcl',
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'-nolog', '-nojournal', '-notrace',
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'-source', scriptPath / 'program_fpga.tcl',
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'-tclargs',
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'-board', board,
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'-bitstream_path', bitstream,
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],
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stdin=subprocess.DEVNULL
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)
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pVivado.wait()
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if pVivado.returncode != 0:
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print(":ERROR: Unable to flash FPGA")
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sys.exit(1)
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def get_serial_from_bdf(id: str) -> str:
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deviceBDFs = get_fpga_bdfs(parsed_args.bus_id)
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if len(deviceBDFs) == 0:
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print(f":ERROR: Unable to obtain Extended Device BDF for {parsed_args.bus_id}")
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sys.exit(1)
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return "TODO"
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def main(args: List[str]) -> int:
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parser = argparse.ArgumentParser(description="Program a Xilinx XDMA-enabled FPGA")
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megroup = parser.add_mutually_exclusive_group(required=True)
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megroup.add_argument("--bus_id", help="Bus number of FPGA to flash (i.e. ****:<THIS>:**.*)")
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megroup.add_argument("--serial_no", help="Serial number of FPGA to flash (i.e. what 'get_hw_target' shows in Vivado)")
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parser.add_argument("--bitstream", help="Bitstream to flash onto FPGA", required=True, type=Path)
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parser.add_argument("--board", help="FPGA board to flash", required=True)
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parsed_args = parser.parse_args(args)
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scriptPath = Path(__file__).resolve().parent
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eUserId = os.geteuid()
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sudoUserId = os.getenv('SUDO_UID')
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isAdmin = (eUserId == 0) and (sudoUserId is None)
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userId = eUserId if sudoUserId is None else int(sudoUserId)
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if not isAdmin:
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print(":ERROR: Requires running script with 'sudo'")
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sys.exit(1)
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if not parsed_args.bitstream.is_file() or not parsed_args.bitstream.exists():
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print(f":ERROR: Invalid bitstream: {parsed_args.bitstream}")
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sys.exit(1)
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else:
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parsed_args.bitstream = parsed_args.bitstream.absolute()
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if parsed_args.bus_id:
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serialNumber = get_serial_from_bdf(id)
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clear_serr(parsed_args.bus_id)
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clear_fatal_error_reporting(parsed_args.bus_id)
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remove(parsed_args.bus_id)
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program_fpga(serialNumber, parsed_args.board, parsed_args.bitstream)
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rescan(parsed_args.bus_id)
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enable_memmapped_transfers(parsed_args.bus_id)
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print(f"Successfully programmed FPGA {parsed_args.bus_id} with {parsed_args.bitstream}")
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if parsed_args.serial_no:
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program_fpga(parsed_args.serial_no, parsed_args.board, parsed_args.bitstream)
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print(f"Successfully programmed FPGA {parsed_args.serial_no} with {parsed_args.bitstream}")
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print(":WARNING: Please warm reboot the machine")
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return 0
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if __name__ == '__main__':
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sys.exit(main(sys.argv[1:]))
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@ -40,6 +40,18 @@ puts "HW device: $hw_device"
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open_hw_manager
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connect_hw_server -allow_non_jtag
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## by default vivado opens a default hw target
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#close_hw_target
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# note: helps view amount of fpgas
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get_hw_targets
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# TODO:
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# when no FPGA is programmed
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# can use id to index into get_hw_targets and program that specific FPGA
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# when you notice a PCI-ID associated w/ the FPGA
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# TODO: how do you determine the ID of the FPGA from the PCI-BDF
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open_hw_target
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current_hw_device [get_hw_devices $hw_device]
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refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $hw_device] 0]
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